What's all this RISC-V stuff, anyhow?

[fabriceo]

Hi, Thank you for the links. Very instructive. Seems each tile will embody an ALU with FP and Vector unit as in the XS3A, let see if they also introduce additional instruction in RV32IM like the 32x32=64 MACC or LSAT or Lextract on 64 bits dual registers.
Also they have hacked the 32bit encoding instruction so that 2x16 bits instructions can be encoded and executed in parallel. let see in practice how the M/R/M+R/M&R actual constrains are handled in the risc-v world.

What is still not clear to me is how the xcore specificities related to hardware threads (aka HARTS now) and the event based model (instead of usual interrupt) will be formalized in the risc toolsets, as the XC compiler and language would be discontinued. Also the concept of "interface" which simplifies inter-tile communication is "lost in translation". No words on the target software framework during the presentation.

[akp]

I hope it works out but honestly I am a little confused as to the value proposition. It seems like a lot of new additions to the ISA just to get back to about where they're already at with XS3? So that means XMOS is also doing a lot of work on a RISC-V compiler to get it to optimally generate the new instructions? Maybe I just don't understand RISC-V but I don't really see what RISC-V is bringing to the table. And it seems like we'll still need to have a pretty deep understanding of tiles (or cores, whatever they're called now) to know the best way to communicate between HARTS, if they can share memory, etc.

Answers some questions but raises more I would say. I honestly have a lot invested in XC and the XS2 ISA so I just hope that toolchain support will continue for a while. I don't want to rewrite code that I spent many years getting to the point of reliability and capability.

[aclassifier]

I have tried to make the theme personal here. From there:

I don’t know how much work it has been to implement the X4, provided you have the X3 with a proprietary instruction set. I guess this to some degree is dependent on whether the X1-X3 is microcoded and if the X4 is so – whether XMOS has gone for a microcoded RISC-V. It looks like the latter is possible (here). I didn’t think the present processors were microcoded. Then going from one microcoded architecture to another one would be less of a chore than any other alternative, I assume? Assuming they haven’t thrown (too m)any babies out with the bathwater?

Any comments?

[aclassifier]

Back to RISC-V...

Recent interview with Mark Lippett, XMOS CEO on this topic.

https://edacafe.com/video/XMOS-Mark-Lip ... media.html

How do we read Mark Lippett's statement that "We have never claimed binary compatibility, we've always asked our customers to recompile their code, that will remain the case as we move from an xcore instruction set to a RISC-V instruction set".

May this indicate that they will indeed port the xC compiler? Or does he disregard the years of xC completely?

[fabriceo]

Hi guys

the VX4A architecture is coming up as we can see in the tensor flow library on GitHub !

seems we ll have a combinaison of standard risc V instructions with plenty of registers, and specific xmos instruction with prefix "xm." that can be bundled in a dual issue mode. VPU is there also, but I hope you guys extended the 32x32=34 to 64...did you keep lsat and lextract/linsert?
do we also have the multi core scheduler, the ssync and msync instructions and the event stuff with waite and channels with in/out ?
please share some info !!!

[upav]

Yes, the VX4B is slowly making its way thru!
Yes, there will be standard risc-v instructions with many of the old xcore instructions as extensions (with the xm prefix). The dual-issue is there but it has completely different packeting rules and is not called dual-issue
VPU's the same length, Isat/extract/insert are still there
XCORE threads are now RISCV HARTs and the resources have come across.
New features were added but I'm not sure if I can talk about them here ;)

[aclassifier]

Ok, so they are not
X4
as I thought, but
VX4 (RISC-V)
and then A and B versions?

GREAT!