USB to I2S port synchronization problem

[matb]

Hello,

I have my own hardware based on the XMOS XU316-1024-TQ128-I24 processor and the SI5351 clock generator (for MCLK = 49.152 MHz). I have implemented USB Audio support and conversion to I2S signal. I used lib_xua and lib_xud libraries for this.

Frequencies up to 384 kHz work correctly but I have a problem at 768 kHz. The DATA signal is shifted relative to the LRCLK signal by two cycles of the BCLK signal (i2s_768_error.png). As a result, the sinusoidal signal at the USB input is converted into a signal divided by 4 (i2s_768_error_2.png).

At first I thought that the processor was having trouble calculating the data to be sent to the DATA line. But even sending a constant number (0xFFFF0000) showed me the same delay on the DATA line.

Now I'm trying to use the sync(port) method to synchronize the LRCLK and DATA lines but I haven't managed to do it yet.

Maybe someone knows how to solve this problem, because maybe I'm trying the wrong methods.

[Ross]

Likely the code cannot keep up at that sample rate - it's outside of the scope of what we validate. How many channels are you trying to drive?

Easy check would be a temporary over-clock of the xcore - say to 800 MHz or so. If it works you'll want the "32" speed grade part (800 MHz) or get optimising ;)

Sync() almost certainly isn't what you want - that will block until the port is completely empty, which you don't want - the code is written to keep the buffered ports full of data.

[matb]

I only control two channels (left and right) or 64 bit (2 x 32) in each I2S sample.

The processor really couldn't keep up in this situation. I made some optimizations and managed to get stable I2S transmission.