[XU316] What exactly does slew rate control in PORT_PAD_CTL? Topic is solved

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
michaelf
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[XU316] What exactly does slew rate control in PORT_PAD_CTL?

Post by michaelf »

Various port attributes can be configured using the PORT_PAD_CTL settings, e.g. enabling the Schmitt trigger, setting drive strength and so on.

Another parameter is slew rate control, where I believe 1 = no slew rate control (i.e. fast edges) and 0 = slow edges.

I've been playing around with these settings using my oscilloscope, measuring edge rise/fall speed as well as slew rate (which is just derived from the rise/fall time) on various clock and data line edges.

Changing drive strength certainly changes the values that I am measuring, but whether I set slew rate control to 0 or 1 doesn't seem to change the measured rise/fall time/slew rate at all.

What measurable parameter does slew rate control affect?
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Joe
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Post by Joe »

Hi, as you've noticed, setting slow slew rate has very little effect. If you are in the highest drive strength modes say 12mA and you are driving a low capacitance load (5pF or less) then you will see the edges do get slower. You would need a high speed scope with low capacitance probe to see this though.

Best to leave slew rate set to default (fast).

Cheers,
Joe
XMOS hardware grey beard.
michaelf
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Post by michaelf »

Thanks for clarifying.