SPDIF not seeming to work at 49.152MHz

[Jcvc]

Hi,

I was trying to use the SPDIF Tx/Rx with a MCLK of 45.1584/49.152MHz instead of 22.5792/24.576MHz, but when doing this, the SPDIF Tx does not work anymore at 44.1/48kHz, however it still 'works' at the higher frequencies (I'm using the USB audio app on the mc-audio-board). If I have set it to 96kHz, then the actual output rate is 48kHz.

I've tried to halve the frequency on the configuration of the clock block in spdif_tx_port_config() and updated the divide value in spdif_tx(), to ensure data rate consistency, however that did not seem to make any difference.

Do you have any suggestion to what might be the problem? Is this just a matter of updating output_word() in order to adjust for the 'new' ratios? Or am I missing something?

Thank you!

[infiniteimprobability]

Hi, I looked at the SPDIF Tx code and it looks like it assumes a clock rate of 48000 * 512 to support 192kHz. So doubling the MCLK would mean it couldn't divide enough to support the lower frequencies, which you are seeing.

Looking at lib_xua, if SPDIF is on the same tile as audio/I2S (which it is on the XU316-MC board) then it re-uses the MCLK clock block for resource efficiency:
https://github.com/xmos/lib_xua/blob/9d ... in.xc#L325

If SPDIF Tx is on a different tile (eg. tile 0) then it uses it's own clock block:
https://github.com/xmos/lib_xua/blob/9d ... in.xc#L657
and
https://github.com/xmos/lib_xua/blob/9d ... in.xc#L256

In the latter case, when the clock block is set up:
https://github.com/xmos/lib_xua/blob/9d ... in.xc#L264
.. it would be possible to add a divide in the clock block (set to 1 for /2) using a setd instruction.

I think (according to https://github.com/xmos/lib_xua/blob/de ... esources.h) that you should have a spare clock block on tile[1] (depending on what else you have added?) so you should be able to work around this by modifying main.xc so that this line:

https://github.com/xmos/lib_xua/blob/9d ... in.xc#L325

to a version that sets up a new clock block (CLKBLK_SPDIF_TX) and sets a divide of 2 (pass the value one since divide is 1 for 0, 2 for 1, 4 for 2 etc.)

void configure_clock_src_divide(xcore_clock_t clk, void port p, unsigned char d); should help which you can find in "xs1.h"

A bit fiddly but I think it should work for your faster MCLK because the IP will work the same, just receive a hardware divided /2 MCLK.

Is Rx working for you at your higher MCLK? I think it should because it actually uses the divided ref clock (100MHz) - https://github.com/xmos/lib_spdif/blob/ ... _rx.xc#L52

[Joe]

Currently the lib_spdif code is limited to an MCLK to FS ratio of 768 max. We can increase that easily if we ensure the clock block used for spdif tx is not shared with anything else. I have done some changes to lib_spdif to make this possible.

https://github.com/xmos/lib_spdif/pull/83

Hopefully this (or something similar) will make it into dev branch eventually.

You can test this on the mc audio board using the example provided in lib_spdif. I've verified this works using 49.152MHz outputting a 48kHz spdif stream.

Pulling it into sw_usb_audio shouldn't be too hard as I don't think the clock block is shared but I haven't looked in detail.

Cheers,
Joe