When designing my L1 board I considered a PSRAM. There are two reasons why I went the SRAM route: 4 or more layers board because those PSRAMs come only in BGA and the balls are small and close (0.75 mm). The other one is the random access of 70 ns. I wanted the external RAM as framebuffer. You either read a burst and then output it at the right time using another port (x8 or x16) thus using more pins or you read it at the right time and latch it. For slow pixel clocks (9 MHz in the case of the PSP LCD) the latch method should work(tm) :).
If you are not planning on using it as framebuffer then it is a good choice because they are simpler to use than SDRAM but they require more pins as the address bus is not multiplexed.
Any external big RAM memory will do.
Development board for XS1-L2
I´m planning to send the data out the 15/16-11. Here it´s my currently 8 mil layout for the xs1-L2.
The external wake-up/sleep pins and booting the first core from Xlink are intentionally left out.
Currently, with 8mil rules 9 signals cannot be connected. I know, some signals need to be polished a little bit, the vias are placed with >=9 mil rules and so it´s not a issue.
I´m not necessary limited by 8mil rules, only i have a fast and not so priced option for 8mil boards.
The reduced pinout notes:
x0d42 unrouted (possible exchanged with X0D42)
x0d27 unconnected (alternative routing access can be possibly made)
X0d39 unconnected (either x0d39 or x0d27 or X0d30 can be connected in layout, x0d30 have two routing access)
x0d28 unconnected (either x0d30 or xd028. x0d30 have alternative routing access)
x0d30 unconnected (see notes above)
x0d26 unrouted (possible exchange with x0d27)
x1d34 unrouted (possible exchange with x1d35)
x1d33 unrouted (possible exchange with x1d32)
x1d31 unrouted (possible exchange with x1d28)
x1d29 unrouted (possible exchange with x1d28)
x1d27 unconnected (only one pin can be connected, x1d26 or x1d27)
x1d26 unconnected (only one pin can be connected, x1d26 or x1d27)
this results in 12 pin - 3 pins (options) = 9 pins unrouted on a 8 mil rule. Port type and relevance not checked.
And finally, the image.
The external wake-up/sleep pins and booting the first core from Xlink are intentionally left out.
Currently, with 8mil rules 9 signals cannot be connected. I know, some signals need to be polished a little bit, the vias are placed with >=9 mil rules and so it´s not a issue.
I´m not necessary limited by 8mil rules, only i have a fast and not so priced option for 8mil boards.
The reduced pinout notes:
x0d42 unrouted (possible exchanged with X0D42)
x0d27 unconnected (alternative routing access can be possibly made)
X0d39 unconnected (either x0d39 or x0d27 or X0d30 can be connected in layout, x0d30 have two routing access)
x0d28 unconnected (either x0d30 or xd028. x0d30 have alternative routing access)
x0d30 unconnected (see notes above)
x0d26 unrouted (possible exchange with x0d27)
x1d34 unrouted (possible exchange with x1d35)
x1d33 unrouted (possible exchange with x1d32)
x1d31 unrouted (possible exchange with x1d28)
x1d29 unrouted (possible exchange with x1d28)
x1d27 unconnected (only one pin can be connected, x1d26 or x1d27)
x1d26 unconnected (only one pin can be connected, x1d26 or x1d27)
this results in 12 pin - 3 pins (options) = 9 pins unrouted on a 8 mil rule. Port type and relevance not checked.
And finally, the image.
- xc1-l2_8mil.png (2.13 KiB) Viewed 5216 times
- xc1-l2_8mil.png (2.13 KiB) Viewed 5216 times
at better resolution.
- xc1-l2_8mil.png (8.1 KiB) Viewed 5215 times
- xc1-l2_8mil.png (8.1 KiB) Viewed 5215 times
If i leave out x1d36, x1d37, x1d38 and x1d39 i could fit all other X?d?? pins on two layer using 8mil rules.
That looks crowded, vias are one ontop of the other one...did I miss something ?
You will have to change the outer via-diamter.
What drill-size do you use? 0.3 mm is often common for a mechanical drill.
What drill-size do you use? 0.3 mm is often common for a mechanical drill.
Probably not the most confused programmer anymore on the XCORE forum.
It´seems overlapping because the resolution. there is enought clearance around the vias.
The drill size is 0.3mm. Gnd/vcc is prerouted and this is the reason why it is crowd.
Vccio need to be routed externally.
I have checked it, it´s not the resolution, it´s a bug in the Sw.
I have made a screenshoot.
Here this look nice (6mil rules, 24mil via, 12mil drill).
Even if this look nicer, with the other i could made a more denser design on a 2 layer board
because gnd and vcc is already routed and don´t need to be routed autside the pcb footprint.
The drill size is 0.3mm. Gnd/vcc is prerouted and this is the reason why it is crowd.
Vccio need to be routed externally.
I have checked it, it´s not the resolution, it´s a bug in the Sw.
I have made a screenshoot.
Here this look nice (6mil rules, 24mil via, 12mil drill).
Even if this look nicer, with the other i could made a more denser design on a 2 layer board
because gnd and vcc is already routed and don´t need to be routed autside the pcb footprint.
That looks way better :). With those rules you get relatively cheap boards, specially if you can keep it down to two layers.
What about the heat from the centrum pad, can it escape in the copper?
(A small Al cooler on the top can maybe be a solution for 2 layer prototypes otherwise)
(A small Al cooler on the top can maybe be a solution for 2 layer prototypes otherwise)
Probably not the most confused programmer anymore on the XCORE forum.
I don't think heat should be a concern according to the L2 datasheet.