USB Audio 2.0 Reference Design 32bit/192kHz support?

[patw]

only the SW on the XMOS side, thanks.

[lilltroll]

To begin with; the XMOS thread "closest" the CODEC chip.

The method:

Code: Select all

 * Module:  module_usb_aud_shared
 * Version: 2v3
 * Build:   6e80ade8555eafea4f657cbe4167db93f1f28861
 * File:    audio.xc

/* I2S delivery thread */
#pragma unsafe arrays
unsigned deliver(chanend c_out, chanend c_spd_out, unsigned divide, chanend ?c_dig_rx)

Seems to support 32-bit mode, there is no @24 in the code, either for CODECisMASTER od CODECisSLAVE

[patw]

So that means it support 32bits by default?

If so, how can the XMOS report to the OS (say OS X) that it can support 32 bit? right now it reports 24bits only.

Thanks,

[misterten]

*push*

[Ross]

So that means it support 32bits by default?

If so, how can the XMOS report to the OS (say OS X) that it can support 32 bit? right now it reports 24bits only.

Thanks,

You need to modify the device descriptors such that it reports itself as supporting 32 bit per sample rather than 24.

I2S cannot support 32bit since it always has an extra clock before data after a LR clock change. You would need to modify the code to support left or right justified mode (of course these are identical for 32bit...)

[Ross]

patw,

I'm intrigued as to why you would want to do so.
The is not an ADC or DAC in the world that can resolve to one part in 4 billion.

Im with heater on this. I guess it could be useful if the stream is passed on to some DSP process.

[MaxFlashrom]

You need to modify the device descriptors such that it reports itself as supporting 32 bit per sample rather than 24.

I2S cannot support 32bit since it always has an extra clock before data after a LR clock change. You would need to modify the code to support left or right justified mode (of course these are identical for 32bit...)

That is not correct: I2S can support two 32-bit left-right samples in one LRCLK frame of 64 BCLK cycles. The MSB of the left and right samples are offset one clock cycle from the change in the LRCLK. The LSB of the left and right samples is allowed to encroach one BCLK past the change in the LRCLK.

See the I2S spec from Philips/NXP here:

http://www.classic.nxp.com/acrobat_down ... I2SBUS.pdf

Incidentally, Burr Brown/TI did attempt a 32-bit DAC http://www.ti.com/product/pcm1795
but I suspect this was just to humour their marketing department and those who have not yet looked at http://en.wikipedia.org/wiki/Johnson_Noise

Regards
Max.

[phalt]

Topic moved to correct forum

[batb]

So that means it support 32bits by default?

If so, how can the XMOS report to the OS (say OS X) that it can support 32 bit? right now it reports 24bits only.

Thanks,

You need to modify the device descriptors such that it reports itself as supporting 32 bit per sample rather than 24.

... how is it done?

[batb]

A suitable 32-bit ADC is the Es9102.
It can be used in mono mode too.
A 2:1 mux is needed.
Not sure how to implement it on the xs1. But obviously I'm a newbie, so calling help from the experts.