Hi,
I'am a newbie of Xc/XMOS programming and I have a question about the clocked output port :?: .
Reading the guide "Programming-XC-on-XMOS-Devices.pdf" at pages 41/43 i have found this code:
# include <xs1.h>
out port outP = XS1_PORT_8A ;
out port outClock = XS1_PORT_1A ;
clock clk = XS1_CLKBLK_1 ;
int main ( void ) {
configure_clock_rate (clk , 100 , 8);
configure_out_port (outP , clk , 0);
configure_port_clock_output ( outClock , clk );
start_clock (clk );
for ( int i=0; i <5; i ++)
outP <: i;
}
and this:
"An output by the processor causes the port to drive output data on the next falling
edge of its clock; the data is held by the port until another output is performed"
But if the output instruction happened before the clock edge the port can buffer ("hold") the data or the output value is only the last i=4? How many value the buffer of each port can store?
In the example on the book the port output is: 0 0 1 2 3 4 4. If there isn't a buffer this output is possible if end only if between each output instruction execution (outP <: i;) there is a clock falling edge.
Thanks
Carlo
Clocked output question
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The data written to a clocked output port is kept in buffer until the next Falling edge. Writing to this buffer (using outP <: i;) has no effect until the previously written data comes out on the next falling edge of 'clk'
Attached JPG is what i got when trying the program in XDE simulator.
The clock frequency is 12.5MHz as indicated in the pdf.
What may be the reason for an extra clock cycle between values 2 and 3?
How can we make sure that the these values are sent out at consecutive Falling Edges of the clock?
Attached JPG is what i got when trying the program in XDE simulator.
The clock frequency is 12.5MHz as indicated in the pdf.
What may be the reason for an extra clock cycle between values 2 and 3?
How can we make sure that the these values are sent out at consecutive Falling Edges of the clock?
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It looks like you simply aren't outputting data fast enough. Do you build
with code optimisation enabled?
Have a look at the generated assembler code to see what's going on.
with code optimisation enabled?
Have a look at the generated assembler code to see what's going on.
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you're right segher.
Optimization was not applied.
Changing the level of optimization results in ouput at consecutive Falling Edges.
I'm not clear with two things below.
The disassembly is shown below
How does the processor know that this resource (outP is associated with a clock)?
The routine which configures the port is this
AFAIK, the first 3 instructions loads r0, r1, r2 with some values. Then it jumps to address '0x94'
How can i see the code at '0x94'?
Optimization was not applied.
Changing the level of optimization results in ouput at consecutive Falling Edges.
I'm not clear with two things below.
The disassembly is shown below
Code: Select all
outP <: i;
0x000100f4 <main+72>: ldw (lru6) r1, dp[0x3]
0x000100f8 <main+76>: ldw (ru6) r0, sp[0x3]
0x000100fa <main+78>: out (r2r) res[r1], r0 *
The routine which configures the port is this
Code: Select all
configure_out_port (outP , clk , 0);
0x000100c6 <main+26>: ldc (ru6) r2, 0x0
0x000100c8 <main+28>: ldw (lru6) r0, dp[0x3]
0x000100cc <main+32>: ldw (lru6) r1, dp[0x5]
0x000100d0 <main+36>: bl (lu10) 0x94
How can i see the code at '0x94'?
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You configured it with one. At assembly level, that is done with some SETC and SETCLK stuff.jai wrote:How does the processor know that this resource (outP is associated with a clock)?
100d4 (the next address in the code, this is a lu10 insn) plus 94 is 10168, so that is the routineThe routine which configures the port is thisAFAIK, the first 3 instructions loads r0, r1, r2 with some values. Then it jumps to address '0x94'Code: Select all
configure_out_port (outP , clk , 0); 0x000100c6 <main+26>: ldc (ru6) r2, 0x0 0x000100c8 <main+28>: ldw (lru6) r0, dp[0x3] 0x000100cc <main+32>: ldw (lru6) r1, dp[0x5] 0x000100d0 <main+36>: bl (lu10) 0x94
How can i see the code at '0x94'?
that is called. I don't know why the disassembler you used doesn't do that addition itself.
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the disassembler doesn't show code in that area.
It ends with
The address i need to see is 0x10168. This may be possible if we can go step by step in the assembler.
But steping in XDE(Version: 11.2.0) is not supported.
Is there any other way to see it?
Thanks for mentioning 'SETCLK', i'll go with that.
It ends with
Code: Select all
return 0;
0x000100fa <main+78>: ldc (ru6) r0, 0x0
0x000100fc <main+80>: retsp (u6) 0x2
But steping in XDE(Version: 11.2.0) is not supported.
Is there any other way to see it?
Thanks for mentioning 'SETCLK', i'll go with that.
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I have no idea how to look at disassembly using the IDE. When using the command line,
you can use xobjdump.
you can use xobjdump.
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so i suppose we cannot see disassembly of 'configure_out_port ' in XDE.
i'll try xobjdump
i'll try xobjdump