Interfacing Quad SPI flash to an XMOS device

[leon_heller]

Someone on the Parallax Propeller forum who had interfaced two Quad SPI flash memory chips to the Propeller seemed rather proud of the achievement and asked this question: "Can any MCU besides Propeller read/write 2 QuadSPI chips simultaneously?" I suggested XMOS, and said I'd have a go at it.

I've designed a little breakout board for the Winbond W25Q16BVSSIG 16 Mbit device, and am having 20 prototype boards made by PCB-Pool. I've just received some chips from Digi-Key. It's intended for the prototyping area on an XC1/XC-1A, or a Sparkfun board. The aforesaid Propeller-head gets 5MHz performance with an 80 MHz clock, I'm hoping for something better. NXP claims 40 MHz for new ARM devices with a hardware Quad SPI interface, and 80 MHz is the maximum. I'll have plenty of spare boards if anyone else wants to play with these devices. This is what it looks like:



I should have arranged the signals more logically on the connector.

[Folknology]

Hi Leon, cool idea

I was looking to try a similar thing using dual quad SPI chips with Amino, but haven't got around to it yet. Unfortunately your layout won't work with my boards and I would need 2 chips on each board also. However I'm interested to see how you get on with them performance wise, its an interesting challenge, you should be able to thrash propeller and also beat the arm perf by doubling up.

regards
Al

[leon_heller]

Thanks, Al.

Let me know what layout you want and I'll design a board with two chips.

[Heater]

Folknology,

...and also beat the arm perf by doubling up.

I haven't really caught up with what newer ARMs can do with SPI RAM/FLASH but I hear rumours that some of them support execute in place. XIP. In which case the XMOS might have trouble matching that
performance.

Ayway octal and I are looking at bringing the ZPU architecture to the XMOS. There is a GCC compiler for the ZPU and we have a ZPU virtual machine to run on an xcore. Performance is not a priority here so much as just being able easily run large C programs with program/data in some external memory. After all there is 7 other threads available on the xcore for the time critical work.

So having big gobs of external RAM via quad SPI in which the ZPU code could operate would be just perfect.

[Folknology]

Leon - Well I was thinking it would need 2 on a board. connector wise it would need an 8 bit port and 2*1 bit ports, so you could make a small board which fits the XK1,XC-X style headers that would make it work with many of the current Xmos boards.

My idea is to connect the 2*4 IO pins to the eight bit port and use the 1 bit ports for CLK and CS (drives both). Then both chips can be read from / written too concurrently using the eight bit port. Some masking may be required for the control codes etc.. but sequential reads could operate using buffered modes perhaps,

What I am not sure about is how fast it can be clocked, external clocking on XS1 is limited to 60Mhz, but given that the CLK is internally generated could we use an 80Mhz clock for read patterns?

if so doubling up could yield 80Mhz minus command overheads on sequential reads.

Also you would need to route the signals a little better for these freqs and think about signal paths/cross talk + use a ground plane etc.. doable with 2 layer though.

*Update it might even be better (for experimentation) to use 3 * 1 bit ports and separately CS0 and CS1 and have a jumper which switches between this mode and the common CS mode. This provides the option to work with them concurrently as one or individually by switching to 2*4 bit ports perhaps.

regards
Al

[leon_heller]

OK, I'll see what I can do. I'll PM you a draft design for checking in a couple of days.

[Folknology]

The jumper idea might be unworkable as the 4 bit ports don't align nicely with the eight bit ports, it would make the design much more complex than it need be what do you think? Stick to the single CS design?

regards
Al

[leon_heller]

Yes, I'm all for keeping it simple at this stage.

[leon_heller]

Here is the draft schematic:

http://www.leonheller.com/images/W25Q_sch.pdf

I can't use attachments with PMs.

[Folknology]

Schematic looks good to me Leon

There are 2 spare 1 bit pins, any ideas for using them?

Put them on a jumper maybe with 3.3v & Gnd

regards
Al