Hi gravis, i am sorry that i did not get back to you earlier and did not respond to your pm of last week.
For a minimalist system this would do:
Code: Select all
XSYS
pin# NAME <--> XMOS
1 5V
2 NC
3 TRST_N MODE2, MODE3
4 GND (Target board GND)
5 TDSRC TDI
6 XL1_UP1
7 TMS TMS
8 GND (Target board GND)
9 TCK TCK
10 XL1_UP0
11 DEBUG
12 GND (Target board GND)
13 TDSNK TDO
14 XL1_DN0
15 RST_N RST_N, TRST_N
16 GND (Target board GND)
17 UART_RX
18 XL1_DN0
19 UART_TX
20 GND (Target board GND)
Make sure that there is a proper reset signal generated on the board when no XTAG is connected.
Also this is more a logic diagram than an electrical one: you might want to add buffers here and there.
The TRST_N of the XTAG2 is not used as such any more in the new tools, you CAN connect it to TRST_N of the XMOS to generate the test reset signal on startup (you still need to generate a proper test reset signal when no XTAG is connected), but it can also be used to toggle the boot select mode pins, which is the new use: if no XTAG is connected it will boot from SPI and if you load code to the board through the XTAG it will boot in 'wait for JTAG' mode. The JTAG state machine reset is not dependent of the TRST_N pin on the XMOS side other than that it must be pulled high at startup, ORing it with the RST_N will satisfy this. (The current tools use a rendezvous between TCK and TMS to reset the JTAG state)
I highly recomment to look at the schematics of several L1 systems to inspire you:
XK-1A (might be a bit confusing with two XTAG connectors for chaining), Minimal L1 system (can't find it back on the site), Corin's L1 DIP module.