GPIO Slice Kit Typos / Errors

[mon2]

Hi. Back in December we reported some errors in the XA-SK-GPIO Slice Kit schematic revision 1v0 that consumed some quality time to debug. To date, we have not seen the corrections posted so will do so here to assist future developers. Please review carefully and let us know if you agree on these findings. More to follow as we continue our current project development.

Reference : XA-SK-GPIO Slice Kit schematic revision 1v0
Date: 17/08/2012

P4 IO Header

Currently:

GPI_2 = Pin 13 on P4 -> A18 on J2 PCIe finger -> X0D19 (Star Slot) -> P4D3 on Tile 0
GPI_2 = Pin 13 on P4 -> A18 on J2 PCIe finger -> X0D41 (Triangle Slot) -> P8D5 on Tile 0
GPI_2 = Pin 13 on P4 -> A18 on J2 PCIe finger -> X1D19 (Square Slot) -> P4D3 on Tile 1

GPI_3 = Pin 14 on P4 -> A17 on J2 PCIe finger -> X0D18 (Star Slot) -> P4D2 on Tile 0
GPI_3 = Pin 14 on P4 -> A17 on J2 PCIe finger -> X0D40 (Triangle Slot) -> P8D4 on Tile 0
GPI_3 = Pin 14 on P4 -> A17 on J2 PCIe finger -> X1D18 (Square Slot) -> P4D2 on Tile 1

GPI_4 = Pin 15 on P4 -> A13 on J2 PCIe finger -> X0D21 (Star Slot) -> P4C3 on Tile 0
GPI_4 = Pin 15 on P4 -> A13 on J2 PCIe finger -> X0D43 (Triangle Slot) -> P8D7 on Tile 0
GPI_4 = Pin 15 on P4 -> A13 on J2 PCIe finger -> X1D21 (Square Slot) -> P4C3 on Tile 1

GPI_5 = Pin 16 on P4 -> A12 on J2 PCIe finger -> X0D20 (Star Slot) -> P4C2 on Tile 0
GPI_5 = Pin 16 on P4 -> A12 on J2 PCIe finger -> X0D42 (Triangle Slot) -> P8D6 on Tile 0
GPI_5 = Pin 16 on P4 -> A12 on J2 PCIe finger -> X1D20 (Square Slot) -> P4C2 on Tile 1

Corrected labels in XA-SK-GPIO schematic should be:

GPI_3 = Pin 13 on P4 -> A18 on J2 PCIe finger -> X0D19 (Star Slot) -> P4D3 on Tile 0
GPI_3 = Pin 13 on P4 -> A18 on J2 PCIe finger -> X0D41 (Triangle Slot) -> P8D5 on Tile 0
GPI_3 = Pin 13 on P4 -> A18 on J2 PCIe finger -> X1D19 (Square Slot) -> P4D3 on Tile 1

GPI_2 = Pin 14 on P4 -> A17 on J2 PCIe finger -> X0D18 (Star Slot) -> P4D2 on Tile 0
GPI_2 = Pin 14 on P4 -> A17 on J2 PCIe finger -> X0D40 (Triangle Slot) -> P8D4 on Tile 0
GPI_2 = Pin 14 on P4 -> A17 on J2 PCIe finger -> X1D18 (Square Slot) -> P4D2 on Tile 1

GPI_5 = Pin 15 on P4 -> A13 on J2 PCIe finger -> X0D21 (Star Slot) -> P4C3 on Tile 0
GPI_5 = Pin 15 on P4 -> A13 on J2 PCIe finger -> X0D43 (Triangle Slot) -> P8D7 on Tile 0
GPI_5 = Pin 15 on P4 -> A13 on J2 PCIe finger -> X1D21 (Square Slot) -> P4C3 on Tile 1

GPI_4 = Pin 16 on P4 -> A12 on J2 PCIe finger -> X0D20 (Star Slot) -> P4C2 on Tile 0
GPI_4 = Pin 16 on P4 -> A12 on J2 PCIe finger -> X0D42 (Triangle Slot) -> P8D6 on Tile 0
GPI_4 = Pin 16 on P4 -> A12 on J2 PCIe finger -> X1D20 (Square Slot) -> P4C2 on Tile 1

The Hardware Manual for this XA-SK-GPIO Slice Kit also has some errors. The following download details our findings.

As a suggestion, each reference to the STAR, TRIANGLE, SQUARE, CIRCLE PCI Express slot connector should be also referenced for clarity with the respective CPU_Tile. This will assist developers to know that, for example, GPI_0 on STAR slot = 4D0_Tile0 but if seated in SQUARE slot = 4D0_Tile1, etc.

Hope this helps someone.

Kumar

Revised attached diagram 1-13-2014

A corrected schematic is posted here (on our company server due to 2 Mb restriction):

http://www.softio.com/doc/gpio_schemati ... ppings.pdf