I have been trying to create a traffic monitor using the XMOS XS1-L16 as the main processing unit. However, when i try access the JTAG tap on the device using a Xtag, I get "Connected to None" within xTimeComposer. I have attached a copy of the board schematic as im pretty sure i have just done something stupid so all comments and suggestions are welcome. Now i am aware the i messed up the MODE pins so SPI probably wont work in their current configuration, but the JTAG should work.
One other thing, i have externally added the pull-up resistor for the open drain on the reset line as i forgot it in the schematic.
Thanks in advance
JTAG Issues with XS1-L16
-
countbadger
- Junior Member
- Posts: 7
- Joined: Wed May 14, 2014 12:45 pm
JTAG Issues with XS1-L16
You do not have the required permissions to view the files attached to this post.
-
mon2
- XCore Legend
- Posts: 1913
- Joined: Thu Jun 10, 2010 11:43 am
A few comments to review:
a) Is your clock source within spec for the respective mode pin configuration ?
b) Are you using a power good reset (voltage supervisor) to properly reset the XS1 core ? Such a component is to monitor the voltage rail and release reset after reaching a threshold. Consider to apply a 0.9 volt reset supervisor and connect to the output of your 1v0 LDO. Actually, we are using in our design a single such device (ie. LDO + power good pin) from Richtek (P/N RT9010).
Also, do review the power consumption of the CPU under the loading condition for your project. Specifically, you may need to increase the current support of your LDO or consider a switching power supply. We are doing this as a safety precaution since we have not yet coded the firmware so allowing for a beefy power rail till we know we can dial it down to reduce the BOM costs.
c) The XS1 datasheet is still recommending to mate the RST_N & TRST_N pins together and drive with an open drain buffer with a pull-up. There is some dialog on the user forums about a possible race condition:
http://www.xcore.com/forum/viewtopic.ph ... ion#p15089
http://www.xcore.com/forum/viewtopic.ph ... ion#p15192
d) Unable to follow your JTAG wiring as it is not the same as the XTAG-2 mapping to the box headers but do check that TDO / TDI are correctly wired. That is, that you are not mating "output to output" and "input to input".
e) The 1V0 led is not recommended to be wired as shown due to the low voltage on that rail. Better to use a 3.3 volt buffer with the CS of the 1.0 volt LDO being used as the input to the buffer and then a LED on the output of that buffer. Specifically, you will then not be loading down that rail and also the LED will be more visible.
f) Be sure your SDRAM is 3.3 volt for the VCC - many SDRAM devices operate at a lower voltage. The SDRAM from ISSI or Micron equivalent as per the SDRAM slicekit is fine at 3.3 volts.
g) On the BOM costs, placement time is costly so consider to gang up the single resistors into resistor networks. If you should mass produce the project, a single resistor pack with 4 resistors (very common in 1206 footprint = 0603 internal) will be considered a single placement "hit" and lower your assembly costs.
a) Is your clock source within spec for the respective mode pin configuration ?
b) Are you using a power good reset (voltage supervisor) to properly reset the XS1 core ? Such a component is to monitor the voltage rail and release reset after reaching a threshold. Consider to apply a 0.9 volt reset supervisor and connect to the output of your 1v0 LDO. Actually, we are using in our design a single such device (ie. LDO + power good pin) from Richtek (P/N RT9010).
Also, do review the power consumption of the CPU under the loading condition for your project. Specifically, you may need to increase the current support of your LDO or consider a switching power supply. We are doing this as a safety precaution since we have not yet coded the firmware so allowing for a beefy power rail till we know we can dial it down to reduce the BOM costs.
c) The XS1 datasheet is still recommending to mate the RST_N & TRST_N pins together and drive with an open drain buffer with a pull-up. There is some dialog on the user forums about a possible race condition:
http://www.xcore.com/forum/viewtopic.ph ... ion#p15089
http://www.xcore.com/forum/viewtopic.ph ... ion#p15192
d) Unable to follow your JTAG wiring as it is not the same as the XTAG-2 mapping to the box headers but do check that TDO / TDI are correctly wired. That is, that you are not mating "output to output" and "input to input".
e) The 1V0 led is not recommended to be wired as shown due to the low voltage on that rail. Better to use a 3.3 volt buffer with the CS of the 1.0 volt LDO being used as the input to the buffer and then a LED on the output of that buffer. Specifically, you will then not be loading down that rail and also the LED will be more visible.
f) Be sure your SDRAM is 3.3 volt for the VCC - many SDRAM devices operate at a lower voltage. The SDRAM from ISSI or Micron equivalent as per the SDRAM slicekit is fine at 3.3 volts.
g) On the BOM costs, placement time is costly so consider to gang up the single resistors into resistor networks. If you should mass produce the project, a single resistor pack with 4 resistors (very common in 1206 footprint = 0603 internal) will be considered a single placement "hit" and lower your assembly costs.