Hi,
assuming I have a system of two XS1-L8A-64 (like the example in the xTimeComposer manual) is there a way to find out how many physical links between the chips are needed to run a given program e.g. the USB Audio MultiChannel Refernce design which is designed to work on two tiles with links between them. This one implements already two 5wire bidirectional links and 1 2wire bidirectional link, I think.
Raphael
How many xLinks are needed? Topic is solved
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rkn
- Member
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- Joined: Tue Nov 18, 2014 6:23 pm
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sethu_jangala
- XCore Expert
- Posts: 589
- Joined: Wed Feb 29, 2012 10:03 am
To extend the processor cores (extended the number of tiles) requires at least one link between the master and the salve node. But the number of links and the link width depends on the speed of data you want to transfer between the tiles. You have 2 wire links and 5 wire links in xCORE architecture.
More details on xCONNECT links is available in the xCONNECT manual in the following link:
https://www.xmos.com/download/public/xC ... 1.0%29.pdf
More details on xCONNECT links is available in the xCONNECT manual in the following link:
https://www.xmos.com/download/public/xC ... 1.0%29.pdf
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infiniteimprobability
Verified - XCore Legend
- Posts: 1164
- Joined: Thu May 27, 2010 10:08 am
The tools only report the number of channel ends used and do not calculate the number and type of links you need (this is a runtime characteristic).
To make a first pass at this work out how many streaming links you have (streaming chan) across the tiles first. This tells you how many permenantly open circuits you will have, each needing a dedicated link.
You must have at least one link between tiles for all other communication (be it chan or interface) across tiles. These will implicitly set up a connection, transfer data and then close it, so can share a links temporally. The communication will still be acknowledged, so nothing will get lost, but may get delayed until the link is free.
The actual performance requirement and number of required links, as ever, will be application specific. If a link is already busy, then a second pair of tasks wishing to communicate will block until it is free..So you will need to work out what the nature of your traffic is that shares the link, to know if it will be acceptable in your app.
For example bursty (eg. passing structs) traffic with latency critical traffic may not play nicely together..
To make a first pass at this work out how many streaming links you have (streaming chan) across the tiles first. This tells you how many permenantly open circuits you will have, each needing a dedicated link.
You must have at least one link between tiles for all other communication (be it chan or interface) across tiles. These will implicitly set up a connection, transfer data and then close it, so can share a links temporally. The communication will still be acknowledged, so nothing will get lost, but may get delayed until the link is free.
The actual performance requirement and number of required links, as ever, will be application specific. If a link is already busy, then a second pair of tasks wishing to communicate will block until it is free..So you will need to work out what the nature of your traffic is that shares the link, to know if it will be acceptable in your app.
For example bursty (eg. passing structs) traffic with latency critical traffic may not play nicely together..
Engineer at XMOS