new I2C library (xTIMEcomposer 14)

[slava]

Hello,
 
I have several questions regarding I2C library.
 
1. I read the following:
 
It is possible to connect both lines to different bits of a multi-bit port as shown in Figure 7. This is useful if other constraints limit the use of once bit ports. However the following should be taken into account:
• On L-series and U-series devices in this configuration, the xCORE can only perform write transactions to the I2C bus.
• On L-series and U-series clock stretching is not supported in this configuration.
• The other bits of the multi-bit port cannot be used for any other function. 
 
The restrictions on reading and clock stretching do not apply to xCORE-200 devices.
 
This sounds good to me because I am going to use the library with an XLF216 device. Has it been tested? I don't see anywhere an example where only one 4-bit port is used. Usually I see the following:
 
port p_scl = XS1_PORT_4C;
port p_sda = XS1_PORT_1G;
 
My questions are:
 
a) If I use the XS1_PORT_4C only, how do I declare port p_scl and port p_sda?
b) does it matter what bit of the port scl and sda connected to?
 
2. I read the following resource usage:
 
Configuration              Pins        Ports              Clocks     Ram     Logical cores
Master (single port) |     2     |  1 (multi-bit) |      0      | ~0.9K |       0
 
Do you believe I can run 3 I2C masters on one core?
 
3. I'd loved to read "Related application notes"
AN00156 - How to use the I2C master library
AN00157 - How to use the I2C slave library
 
But apparently they are not available.
 
Thanks,
Slava

[Thomas]

Hi Slava

Here are the answers (denoted by A>) to your questions:

a) If I use the XS1_PORT_4C only, how do I declare port p_scl and port p_sda?
A> You declare it like a single port and pass it into the function i2c_master_single_port which is described on page 10 in https://www.xmos.com/download/private/l ... rc1%29.pdf
b) does it matter what bit of the port scl and sda connected to?
A> Yes. you tell the function i2c_master_single_port the bit position with the following parameters: unsigned scl_bit_position, unsigned sda_bit_position
 
2. I read the following resource usage:
 
Configuration Pins Ports Clocks Ram Logical cores
Master (single port) | 2 | 1 (multi-bit) | 0 | ~0.9K | 0
 
Do you believe I can run 3 I2C masters on one core?
A> Yes. It is a distributed task so doesn't take up any cores of its own unless
you communicate with another tile. In that case you could combine them on one
core.  Each task would use the core at the transaction level (i.e. would occupy
it for one read/write transaction before possibly yielding to another I2C
master task).
 
3. I'd loved to read "Related application notes"
AN00156 - How to use the I2C master library
AN00157 - How to use the I2C slave library
 
But apparently they are not available.
A> Correct. They are not available yet.