It seems that there is a maximum time allowable between the VDDIO rail reaching its target voltage and the VDD rail reaching its target voltage. If this time is too long (>100ms seems to cause problems) the XMOS processor(s) refuse to boot even if all power and reset specifications in the datasheet are met.
What is this maximum time? And could it please be put into the power specification in the datasheets.
VDD / VDDIO power sequencing
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Redeye
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The VDDIO supply must be within specification (3.0V - 3.6V) before the VDD (core) supply reaches 0.4V. The VDD (core) supply should ramp monotonically (constantly rising) from 0V to its final value (0.95V - 1.05V) within 10ms to ensure correct start-up. The VDD (core) supply should be capable of supplying at least 300mA for an L6/8-64 and 600mA for an L8/10/12/16-128 device assuming they may be operating at full capacity.