SDRAM Slice on xCORE-200 USB sliceKIT Topic is solved

[aneves]

Hi infinteimprobability,

I bought the kit from digikey and my region is Boston, Massachusetts, USA. I very much appreciate your speedy responses and your effort to correct the situation. I see that the site has been updated to reflect that the SDRAM sliceCARD is not compatible with the cCORE-200 USB sliceKIT - Thank you for fixing the documentation so quickly! The board selector pdf should get updated too though.

After discussing with my colleagues, we've decided to stick with this dev board since there are other things I need to evaluate with this platform for our project. As for accessing SDRAM with the XMOS chip, we've decided to pursue a hardware solution using either a CPLD or FPGA as the interface between the chip and SDRAM. That seems to be more typical in these cases. If anyone has any other opinions or experience on that, I'd love to hear them.

[infiniteimprobability]

I see that the site has been updated to reflect that the SDRAM sliceCARD is not compatible with the cCORE-200 USB sliceKIT - Thank you for fixing the documentation so quickly! The board selector pdf should get updated too though.

Yes - well hopefully others can avoid the pain you experienced.
The board selector pdf is actually for first generation (XS1) rather than xCORE200, but I can see how that can be misleading as both generations have a USB member.. I wonder if the old guide should be put out to pasture?

After discussing with my colleagues, we've decided to stick with this dev board since there are other things I need to evaluate with this platform for our project. As for accessing SDRAM with the XMOS chip, we've decided to pursue a hardware solution using either a CPLD or FPGA as the interface between the chip and SDRAM. That seems to be more typical in these cases. If anyone has any other opinions or experience on that, I'd love to hear

I can see how that would help development - you could perhaps get around the SI issue of the slicekit by having the fast signals decoupled via the FPGA which would act as a memory server. Seems like a big extra expense for a product though - the SDRAM controller for XMOS does work and is pretty efficient on I/O - 1 x 16b port + 4 x 1b ports so personally I'd focus on spinning a board with decent SI and nice point to point trace length matched and impedance matched connections to the SDRAM. But I don't know the architecture of the system so may be missing something..

[NickGManc]

Just a quick question - does lib_sdram-3.0.2 work with XS1 devices. The documentation doesn't mention any limitation in this respect. I have an XS1 slicekit and SDRAM card which work fine with the old SDRAM library and the 13.2.0 tools, but fails with the new lib_sdram and 14.1.2 tools.

Has anyone got this or a similar combination to work? It is frustrating as I have a design ready to go but don't want to commit to manufacturing until I can be sure the SDRAM will actually work.

[aneves]

Can you define what "fails" means in the context? Does it fail to build? Fail to write/read from SDRAM?

You'll probably want to start a new thread if you haven't already since this one has been marked solved. I don't know if anyone else is really paying attention to it.