Hallo XMOS community
I recently got knowledge to Xcore multi-threaded uC and it sounds really interesting.
I read about functionality and I'm interested in SPI-control of multiple slaves (sensors etc.).
If i understood it the right way ... is it possible to assign SPI functionality to individual pins of XCORE-device?
So my question is:
Is it possible to build up multiple SPI-channels (MISOi,MOSIi,CLKi) that are controlled by individual corei?
From documentation documents, ANs and forum search i couldn't clearify this question ... maybe because i'm quite new to XMOS.
Thanks in advance.
Best regards
Timbo
Multi channel SPI
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Hi and welcome to XMOS forums
SPI is implemented in software, and can use any available I/O ports, provided they are 1bit wide. If you use the XMOS SPI library (https://www.xmos.com/support/libraries/lib_spi), a SPI master task has no global state so will instantiate multiple times easily:
Each SPI master task can have multiple clients (each client connected via one interface from either the i1 or i2 array) and each task can serve multiple SPI devices on the same bus with different select lines (individual ports of the p_ss array).
Examples (tests) that come with the SPI library don't seem to include a multi-task one, but if you look at the ones that are in there now, it should become clear what to do.
https://github.com/xmos/lib_spi/tree/master/tests
For documentation, refer to application note AN00160 and the SPI library documentation:
https://www.xmos.com/support/appnotes/AN00160
https://www.xmos.com/support/libraries/lib_spi
SPI is implemented in software, and can use any available I/O ports, provided they are 1bit wide. If you use the XMOS SPI library (https://www.xmos.com/support/libraries/lib_spi), a SPI master task has no global state so will instantiate multiple times easily:
Code: Select all
in buffered port:32 p_miso1 = XS1_PORT_1A;
out port p_ss1[1] = {XS1_PORT_1B};
out buffered port:32 p_sclk1 = XS1_PORT_1C;
out buffered port:32 p_mosi1 = XS1_PORT_1D;
clock cb1 = XS1_CLKBLK_1;
in buffered port:32 p_miso2 = XS1_PORT_1E;
out port p_ss2[1] = {XS1_PORT_1F};
out buffered port:32 p_sclk2 = XS1_PORT_1G;
out buffered port:32 p_mosi2 = XS1_PORT_1H;
clock cb2 = XS1_CLKBLK_2;
par {
spi_master(i1, 1, p_sclk1, p_mosi1, p_miso1, p_ss1, 1, cb1);
spi_master(i2, 1, p_sclk2, p_mosi2, p_miso2, p_ss2, 1, cb2);
}
Examples (tests) that come with the SPI library don't seem to include a multi-task one, but if you look at the ones that are in there now, it should become clear what to do.
https://github.com/xmos/lib_spi/tree/master/tests
For documentation, refer to application note AN00160 and the SPI library documentation:
https://www.xmos.com/support/appnotes/AN00160
https://www.xmos.com/support/libraries/lib_spi