Hey everyone,
This is my first post so any support is welcome. I'm looking for a way to use the XUF216-512 with an eMMC that only supports 1.8V I/O. I'd be more than happy to do so without the use of level converters (that add delay, increase board size, costs, etc). I see that the VDDIOT should work with 2.5V, but am not sure about VDDIOL and VDDIOR or if any of them works with 1.8V.
Has anyone tried such? Cheers!
Does the XUF216-512 support 1.2-2.5V on VDDIOL/VDDIOR/VDDIOT
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dexterelu
- New User
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henkVerified
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Hi dexterelu,
I am afraid that the xCORE200 chips are not characterised or tested for 1V8.
If you run a domain that supports 2V5 at 1V8 they may work. This may be device dependent, and probably slower than 2V5.
Cheers,
Henk
I am afraid that the xCORE200 chips are not characterised or tested for 1V8.
If you run a domain that supports 2V5 at 1V8 they may work. This may be device dependent, and probably slower than 2V5.
Cheers,
Henk
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dexterelu
- New User
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Hey Henk,
Thank you for your quick reply. I guess that a few external pull-up resistors would work with an open-drain output. The only thing I'm not so sure about how well would the XUF216 read the input. The datasheet says it requires a minimum of 2V input for high. So 1.8V wouldn't normally cut it. I'm assuming this is true for a 3.3V power line.
I'm pretty sure I can do some manual tests with a pot and see just where the XMOS sees the input as high, but that's for DC. I'm trying to go as high as 10-25MHz. Has anyone else experimented with the XUF216 outside of the spec sheet?
Thanks again!
Thank you for your quick reply. I guess that a few external pull-up resistors would work with an open-drain output. The only thing I'm not so sure about how well would the XUF216 read the input. The datasheet says it requires a minimum of 2V input for high. So 1.8V wouldn't normally cut it. I'm assuming this is true for a 3.3V power line.
I'm pretty sure I can do some manual tests with a pot and see just where the XMOS sees the input as high, but that's for DC. I'm trying to go as high as 10-25MHz. Has anyone else experimented with the XUF216 outside of the spec sheet?
Thanks again!
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mon2
- XCore Legend
- Posts: 1913
- Joined: Thu Jun 10, 2010 11:43 am
I think you are taking a high risk in your open drain approach.
Here are some notes found on the TI website on the use of open drain methods:
Reference article:
http://www.ti.com/lit/an/scea035a/scea035a.pdf
Instead, why not apply a small footprint bidirectional level shifter for the best results ? For example,
https://e2e.ti.com/support/interface/vo ... 1/t/343093
http://www.ti.com/product/TXS0206
Keep in mind that these are FET based level shifters so they have little to no drive ability. That is, keep the PCB traces short and do not even think about using any cabling - been there and done that and killed a lot of time with poor results. However, on a positive note, Intel is using similar devices for their SD card interface on the Galileo project for proper level shifting in/out of the CPU port pins. The trick here is to keep the PCB traces short as possible.
Working with flip chip packages, etc. is not a simple chore so be sure to review the PCB traces and widths and may even require the use of via in pad PCB services. Via in pad support will escalate the PCB production costs a bit. Can share some reliable PCB mfr details on demand who support this service.
Here are some notes found on the TI website on the use of open drain methods:
Reference article:
http://www.ti.com/lit/an/scea035a/scea035a.pdf
Instead, why not apply a small footprint bidirectional level shifter for the best results ? For example,
https://e2e.ti.com/support/interface/vo ... 1/t/343093
http://www.ti.com/product/TXS0206
Keep in mind that these are FET based level shifters so they have little to no drive ability. That is, keep the PCB traces short and do not even think about using any cabling - been there and done that and killed a lot of time with poor results. However, on a positive note, Intel is using similar devices for their SD card interface on the Galileo project for proper level shifting in/out of the CPU port pins. The trick here is to keep the PCB traces short as possible.
Working with flip chip packages, etc. is not a simple chore so be sure to review the PCB traces and widths and may even require the use of via in pad PCB services. Via in pad support will escalate the PCB production costs a bit. Can share some reliable PCB mfr details on demand who support this service.
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henkVerified
- Respected Member
- Posts: 347
- Joined: Wed Jan 27, 2016 5:21 pm
Hi,
I second mon2's warning about open drain - it will be neither fast nor pretty.
To answer your question: V(IH) for 2.5v will be lower; probably 1.7V or so. I think this may be too high for 1.8V logic where V (OH) is as little as 1.35V? (according to http://m.eet.com/media/1102811/FigSB3.gif)
Cheers,
Henk
I second mon2's warning about open drain - it will be neither fast nor pretty.
To answer your question: V(IH) for 2.5v will be lower; probably 1.7V or so. I think this may be too high for 1.8V logic where V (OH) is as little as 1.35V? (according to http://m.eet.com/media/1102811/FigSB3.gif)
Cheers,
Henk