external flash device - flash success, boot noot. Topic is solved

[DemoniacMilk]

For connecting an external flash to an explorerKIT, the xn file was adjusted to use the external instead of the onbard flash (adjusted device type, QSPI to SPI, Ports),

When flashing the device, data is transfered. I conected a logic analyzer and from what i saw the process is: page write, poll SReg until page write is done, read page for verification. I did not verify the data sent manually but xtimeComposer studio prints "[...] Site 0 has finished successfully." so I guess all is good.

However, the device is not booting and from what I see there is no communication at all.
Do I need to adjust more than just the xn file?

[infiniteimprobability]

Hi - you're going to need to change the boot pins too so that the boot rom is steered to using the SPI (single data line) loader. Remember that the initial bootloader is in ROM and it's not until the second stage bootloader is loaded that anything in your software can have an effect.

See section 8 - basically it's pins X0D4..6 which need to be set properly. These are not brought out to headers for SI reasons (it would make stubs on the QSPI lines) so you'll need to pick these up on the pads on the unpopulated QSPI device U2

[DemoniacMilk]

Hello, thanks for the advice, I was not aware of that.
I checked the xTIMEcomposer user guide, xmos programming guide, xn specs, xflash command-line manual and libflash api documentation, but wasn't able to find to find additional information. What document were you refering to?

Ou and may I only use specific pins? Cause my external flash is connected to the ports 1M..1P (D36..D39) as I wanted to not change the devkits hardware.

[infiniteimprobability]

Oops - sorry. I was referring to the device datasheet. That's where you'll find all of the chip details.

[DemoniacMilk]

Okay so it seems like I either need to replace the boot loader in the OTP or the onboard-flash device (I wanted to avoid changes like these, in case someone else grabs a devkit for some tests).
I'll go ahead and replace the onboard flash IC.

[infiniteimprobability]

Okay so it seems like I either need to replace the boot loader in the OTP or the onboard-flash device

The first stage bootloader (which loads in the second stage bootloader from the external boot source) is in ROM (mask ROM) on the chip. This bootloader can support different data sources (SPI slave, master, link, OTP) and is steered by the boot mode pins, and presence of an OTP boot image.

By defualt, the OTP is blank so I don't think you need to worry about burning OTP (which is a pain for development as it's a one way ticket) although it would be a way of changing the boot process if your mode pins were not accessible. It's way simpler in this case to add boot straps to change the built in ROM boot mode to use SPI master, so plan B from above makes sense here

[larry]

Also bear in mind that for xCORE can only SPI boot from ports 1A, 1B, 1C and 1D (MISO, SS, CLK and MOSI, respectively). That is the chip's boot ROM.

[DemoniacMilk]

yup I figured that out based on what infinite said.
Thanks for pointing it out that clearly tho, might help someone in future.