Watchdog

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
lorenzochiesi
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Posts: 25
Joined: Mon Sep 05, 2016 4:20 pm

Watchdog

Postby lorenzochiesi » Tue Jan 03, 2017 3:16 pm

Hi all,

I'm developing an industrial ruggeddized USB "audio" acquisition interface intended for continuous vibration monitoring on industrial machine.
Considering that the acquisition interface will be self powered and will be connected to an embedded PC where no human will access I need to keep in consideration the possibility that the USB stack code or other code in XC200 device fail resulting in an unrecoverable lock of the USB communication.
For this reason I need to include a Watchdog timer.
Seems to me that XMOS device don't have this integrated feature so I'll use an external device like the STWD100NYWY3F from ST microelectronic. This kind of chip has an input that uC should toggle within cerain time and an open-drain output to be connected to the reset pin of the device in parallel to other reset source like a power_good and external reset coming from XSYS connector (JTAG).

The obscure point is how to add this functionality without interfere with XSYS JTAG programming and debugging feature!

XC200 has 2 reset: RST_N and TRST_N that datasheet suggest laconically to short together...I suppose that RST_N will reset the uC wile TRST_N will only reset the JTAG interface. Is it correct?

So is correct to design a reset circuit that:
- in case of PGOOD or JTAG_RST low will keep low both the RST_N and TRST_N pins
- in case of WDT reset low will keep low only the RST_N pin leaving TRST_N out of reset?
Will this solution prevent that Watchdog reset disturb the programming and the debugging from XSYS JTAG interface?

Of course another solution is to connect the EN pin of Watchdog chip to uC. In this way the Watchdog can be normally disabled at power on and being enabled by uC code.
Anyway this seems a more dangerous solution...

Many thanks for your consideration on this subject

Lorenzo
henk
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Posts: 346
Joined: Wed Jan 27, 2016 5:21 pm

Postby henk » Wed Jan 04, 2017 9:35 am

Hi Lorenzo,

You are correct that RST_N resets the chip, and TRST_N puts the JTAG circuit in a known state. You may have noticed that in the smaller pin count packages, only one pin is used that is bonded out to both pads.

Both RST_N and TRST_N must be low when power comes up.

If the chip ends up in an unknown state, you should really pull both down too in my opinion; it won't hurt to reset the JTAG state machine, and it will hurt if some part of your chip is in an unknown state.

So unless there is a reason that you want to issue a separate TRST (for example for some production testing), I would tie them together and create a wired or between (a) POR, (b) XTAG reset and (c) watchdog reset. Just put the XTAG reset through an open-drain buffer.

Cheers,
Henk

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