Ref Clock output on pins ?

[vanjast]

As I start some serious L2 stuff, a question or 2.

I would like to have 3 clock outputs, 100Mhz, 50Mhz and 25Mhz, driving a CPLD

1) Can I apply more than one output pin to a single clock-block. If so, can the pins have different frequency dividors.

OR
2)I'd imagine that I'd have to use 3 clock-blocks for this.

In either case, would all 3 clock o/ps on the pins be in sync with each other.
I realise they're derived from the reference clock, but would the timing tolerances be tight enough so as to called them mutually synced.

I'm concerned about this as I'd like to generate a 10nS strobe signal, through a 5nS CPLD, so any 'out-of-sync' clocks must be avoided.

Thanks for any help/advice
Van
edt: I wish Xmos would produce datasheets like PIC and Intel.. etc, wrt functional diagrams and timing charts :?: :?:

[jason]

edt: I wish Xmos would produce datasheets like PIC and Intel.. etc, wrt functional diagrams and timing charts

I shall pass your comment/feedback on to our documentation team.

[Woody]

2) Each of the three frequencies will need to be generated from a separate clock block.

Note however that an undivided reference clock can not be output from a port. If you really need a 100MHz output you'll need to change the reference clock to 200MHz and divide it by 2 in a clock block before outputting it. Be careful when changing the reference clock from 100MHz because this will change all the timer constants used on the device.

The different clocks will launch at the same time (because they're derived from the same clock), but there will be some skew driving out of the chip. See http://www.xmos.com/system/files/xs1-port-timing.pdf for more details. It depends what you're doing with the clocks to as to whether they are closely timed enough. FWIW, I would not clock one DFF on one of these clocks and expect it to be reliably captured in the CPLD on the following edge of a different clock.

[vanjast]

Thanks.. I been reading a bit more (sifting through the garbage).
That port timing pdf looks more concerned about input clock signals than anything else.

I'll probably have to slow the clock down, but I can double up on the 'hardware' to achieve the same result. This is not a problem as it can be implemented in the CPLD with anti-phase clocking.

Ah well!!, I'll just have to go get myself a 100Mhz storage scope (@13K ZAR) - always wanted one - just have to hide it from the wife :mrgreen:

Actually how much are these over there ?
:D

[f_petrini]

For hobby use I can recommend a Rigol DS1052E scope for about 400 USD including shipping from China.

It's a 50MHz (1GS/s) scope but can easily be "upgraded" to a 100MHz scope by reprogramming the serial/model number.
Changing the Rigol DS1052E to DS1102E using USB , the dummy guide
I haven't modified my own scope yet but I hear that the modification works perfectly...

[vanjast]

That stuff looks great..and a lot cheaper too... thanks for the tip
:D