XS1-G4 supercomputing array (with memory)

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DrMario
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XS1-G4 supercomputing array (with memory)

Post by DrMario »

Version: 1
Status: Just an idea
License: BSD

I am planning to create the XS1-G4 array for supercomputing application, mostly for integer computing (such as data calculation / software-based floating point).
The board itself would contain up to 8 to 32 XS1-G4 chips together, along with its own high-speed DRAM chips (DDR-II - maybe much faster, still determining...)

with the main host controller - a FPGA or another XS1 chip with the fiber optic connection down to the PC via PCIe. The first test application probably would be Artifical Intelligence, or something similar (that otherwise would overwhelm the x86 CPUs). While I can do away with AMD Radeon HD 4670 I have, I perfer to have something more easier to control (variable programming run-time environments) and I just like to build something that would benefit me (and possibly the others - when I build more board, I will be putting it in my own supercomputing rack - I want to start out with 25 GIPS - if I can get to my goal of having 320, it may go to 800 GIPS or faster.)
I may try to get around to prototyping the whole thing by Summer if I can be able to do so. (Hobby costs more money - but hey, I enjoy doing it!)
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Mamma-Mia, It's a-chip! It's XS1-G4, a-wonderful!
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TonyD
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Post by TonyD »

What more can I say.. awesome project :)

Are you planning for each XS1-G4 to have its own SDRAM ?
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DrMario
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Post by DrMario »

Yeah, I am going to use SDRAM, because they usually can pipeline the data pretty quickly (some have up to 16 banks - allowing 1.2 GB/s). I was planning on DDR-I / II, until I found out it ain't flying, so I had to stick with it. Why have its own RAM? It's to reduce the chance of the XS1 chips from fighting each other for the RAM request / storage from the main controller FPGA (ECP2 / ECP3)'s DDR II memory containing the supercomputing instructions. Why isn't it going to fly? Some told me that it can only do 100MHz clocked signaling on all pipelines (I was a bit surprised because some pipelines can do 50GB/s as mentioned in datasheet).
Mamma-Mia, It's a-chip! It's XS1-G4, a-wonderful!
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promptcritical
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Post by promptcritical »

Other than assembling a machine, what is the gaol. Not that assembling a monster machine isn't a worthy goal, but eventually a machine is only as good as it's used for.
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DrMario
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Post by DrMario »

Yeah... Sorry, I was busy and I didn't feel like I was up to that ever since the disaster struck in Japan. I may try to get at it, I hope.

The goal is to try and do simple things first - like doing integer and fixed points first before I get up to the point that I would try and hack the internal software configuration so it would be able to perform the floating-point data or use another processors with it. Forcing the XS1-G4 to execute the workload out-of-order would take lot of work, but if succeed, it would be able to keep the execution time shorter (it got enough logic circuitry on-die that it would be possible to turn it into an Out-of-Order-Execution processor, but it's the pick-and-decode logics that's holding it back in a way).

And Yep, SDRAM will be used, unfortunately, due to the limitation of the IO pipeline frequency (50 or 100MHz)... But if I still want insanely high speed memory read & write throughput, I may have to use the FPGA (Cyclone III) to allow the usage of higher-frequency memory (like DDR-II 533 - 800MHz) to keep up with the XMOS processors.
Mamma-Mia, It's a-chip! It's XS1-G4, a-wonderful!
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promptcritical
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Post by promptcritical »

As bad as i feel horrible for anyone in Japan, or have family and friends there. As a former nuclear operator,I feel especially bad for my nuclear operator brothers(and sisters) who are literally dying from soaking up massive rads while trying to handle three partial core meltdowns, a leaking cooling pool, multiple hydrogen explosions, I can't even name it all.

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DrMario
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Post by DrMario »

Yea, that's what I felt. It was a horrible mess over there at TEPCO's Fukushima Daiichi NPP complex. I did saw the picture on the web, it was real unsettling... (But at least the internal dome is still intact, thankfully... The internal core? I can't say.)

And, I am real hopefully that they can put up solid plan in clean-up efforts and to be able to get with the containment quickly before my wife would decide to come back (she chose to leave Japan - she knew that risk pretty well, so I felt she made a right choice to). I also have been keeping my eyes on TEPCO website and Wikipedia to see what's currently going on - as some of my friends are still in Japan. And, I am especially glad that you really understand given your position as a nuclear power plant operator.

*** Please pray for Japan ***
Mamma-Mia, It's a-chip! It's XS1-G4, a-wonderful!
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DrMario
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Post by DrMario »

I guess I may have to suspend this project... Money's an issue right now. T____T
And, I also doubt anyone appreciate this one as well (maybe there's no point as everyone do have
AMD Radeon HD and NVIDIA GTX video cards by now).

I get discouraged too easily, so maybe I did hit the wall. (or did I? Eh, maybe not so much...)
Mamma-Mia, It's a-chip! It's XS1-G4, a-wonderful!
Oskar
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Post by Oskar »

isn't the project you had planned closely related to the XK XMP 64 development board now available at XMOS? The next step(s) from my point of view would be: 1. port Linux (as a legacy OS sample), 2. have some dedicated OS for it. No?
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DrMario
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Post by DrMario »

I may start doing the PCB design soon enough - just need to pick the package (preferably the BGA package)
so I can fit on the board nicely, to afford the best IO datapath. Yup, it's kinda based off XMP-64 - only they will have their own RAMs as even the transputers Txxx series are still affected by Von Neumann bottleneck when you build the system from basic hardware to very sophisticated hardware.

And, yea - I may try Linux port (uCLinux) to try and fit onto the firmware flash SPI (it depends on how much I can hold onto it. I may include the SDRAM, and include the GDDR3 onto the FPGA to alleviate the Von Neumann bottleneck that have been plaguing the PCs since last decade (early 00's) and emulating the 68k or x86 isn't impossible - only very difficult due to the nature of the way the Vogon Banana Codes (the XS1's ISA) is handled here.

I apologize if I sounded stupid the last few weeks ago.

Anyways, there's also the power supply issue - if I add in more and more XS1 chips, it will stress the DC rail - so choose the power supply wisely if you do the same thing. I would have to get 600 watts PC power supply to give me some foot room here with the DC rail. (putting the vampire tap on 12V is best as it is also performed on ATX motherboard, thus relieving stresses on the power supply by letting the switchmode voltage regulator take 12V down to 3.3 volts DC and take the punishment from there - AMD Phenom II processor in my computer here can suck up to 90 A, just to give ya an idea of the power consumption and the reason for 12V vampire taps.).
Mamma-Mia, It's a-chip! It's XS1-G4, a-wonderful!