Clock Rates

[jonathan]

Confused again... sorry.

The Programming Manual states:

configure_clock_rate(clock clk, unsigned a, unsigned b)

This function configures a clock to run at a rate of b MHz. If the specified rate is not supported by the hardware, an exception is raised. The hardware supports a rate of 100MHz and rates of the form (50/n)MHz where n is in the range 1 to 255 inclusive. A 100MHz reference clock is required for correct operation.

Does this mean the slowest speed I can clock a port at using an internal clock is 196KHz? (50/255 MHz). And what values of a and b am I allowed to feed into this function...?

Taking a look at the waveform viewer I seem able to feed a bunch of other values into the simulator and simulate clock speeds below this, which is rather misleading (in my opinion). Did I misunderstand something?

Also, can I check that I am allowed to clock ports slower than this using an external clock?

Thanks.

[Woody]

Does this mean the slowest speed I can clock a port at using an internal clock is 196KHz? (50/255 MHz).

The slowest output from a clock block dividing a 100MHz reference clock is 50MHz/255=196kHz.

a and b are unsigned, so they can take any 32 bit unsigned value. However if they do not divide nicely to an exact frequency achievable using the reference clock you will get an error. (Use configure_clock_rate_at_least() or configure_clock_rate_at_most() to just select a close value).

Note that in the 10.4 tools, there is now support for non 100MHz reference clock use with these functions, so you can have internally generated reference clocks lower than 196kHz if a lower ref clock is used. (Thanks for pointing out the comment: a bug has been raised on the documentation for this to remove the 100MHz restriction comment.) Note however that changing the ref clock will have a knock on effect of reducing the accuracy of timing on ports clocked by internal clocks. Also a reference clock change will have an effect on all timers in the system.

Also, can I check that I am allowed to clock ports slower than this using an external clock?

Yes you can.

[jonathan]

Does one have to set-up loopback ports with physical wires/connections or can ports be configured to loop-back in software/assembler?

[Andy]

There's loopback in the simulator but if you want to do it for real on the chip you'll have to wire them up.

[larry]

Taking a look at the waveform viewer I seem able to feed a bunch of other values into the simulator and simulate clock speeds below this, which is rather misleading (in my opinion).

If you can describe a specific case when this happens, please let us know - that would be a bug in the simulator.

Here is my test which shows correct behaviour on 10.4 tools:

Code: Select all

$ cat a.xc
#include <platform.h>
clock b = XS1_CLKBLK_1;
clock c = XS1_CLKBLK_2;
int main()
{
  set_clock_div(b, 255);
  set_clock_div(c, 260);
  start_clock(b);
  start_clock(c);
  while (1);
}
$ xcc -target=XK-1 a.xc && xsim --vcd-tracing '-xe a.xe -o a.vcd -clock-blocks -cycles' -t a.xe

In the VCD clock block c wraps to 4 as expected - screenshot attached

[Julien]

Hi all,

On the same topic, is it possible to cascade clock blocks? With the divisor limitation, I would like to make a clock block as a prescaler (let's say 2MHz == 100/50) and a second one as a slow clock block (let's say again 10kHz == 2MHz/200).

Is that possible with XMOS? I did not find any hints in the docs.
If not, do you have a solution to generate slow clocks on XMOS (except bit-banging of course!) As said before, minimum clock is ~196kHz and I need much less, with non-blocking access (I love serialization! :oops: ). Oh, and I need all the 8 threads of course ;-)

Sorry to hijack the thread, I'll make another one if I am off-topic.

Sincerely,
Julien

[jonathan]

Hi all,

On the same topic, is it possible to cascade clock blocks? With the divisor limitation, I would like to make a clock block as a prescaler (let's say 2MHz == 100/50) and a second one as a slow clock block (let's say again 10kHz == 2MHz/200).

Is that possible with XMOS? I did not find any hints in the docs.
If not, do you have a solution to generate slow clocks on XMOS (except bit-banging of course!) As said before, minimum clock is ~196kHz and I need much less, with non-blocking access (I love serialization! :oops: ). Oh, and I need all the 8 threads of course ;-)

Sorry to hijack the thread, I'll make another one if I am off-topic.

Sincerely,
Julien

You can use an external oscillator for a lower clock frequency (you can divide down a clock signal received from a pin - I think the logic is that this serves as an additional reference clock).

I also came up with a rather more comical solution of creating cascading clocks by driving a slow clock onto an output pin, looping it back to an input pin and then dividing down this input pin.

Someone else will be able to provide example code. I don't think you can cascade clocks within software - I think if you want a <196kHz clock you're going to need a HW solution.

[snowman]

You can use an external oscillator for a lower clock frequency (you can divide down a clock signal received from a pin - I think the logic is that this serves as an additional reference clock).

Only internal clock can be divided down. You cannot divide down an external clock.

[jonathan]

You can use an external oscillator for a lower clock frequency (you can divide down a clock signal received from a pin - I think the logic is that this serves as an additional reference clock).

Only internal clock can be divided down. You cannot divide down an external clock.

I stand corrected.

So is the only way of driving a pin below 196kHz to use a slow external clock at exactly the frequency you require? (Or using a slower external reference clock for the whole chip?).