My BitScope samples at 20 MS/S, so I'd have to make a loop to see if I could use the sub-sampling at 500 MS/s. So I have no picture for you at the moment. That's what started this, I wanted to have a look, to see the signals. It's always nice to see. I must admit, I have ben looking for higher sampling rate USB scopes. (PICOSCOPE 2208B does 1GS/S.. and I could afford it)
I have double sets of xCORE-200 eXplorer boards and WiFi sliceCARDs and I have tried all permutations with and without load on PCI_CLK and I can not see any different behaviour. They simply never pass the stop point when loaded, always work fine and returns "Hello World X" over the air when not loaded.
Thinking about printing that collides with the SPI bus, what is the XMOS thinking here? Let's say that the SPI bus runs on one core alone (I know, it doesn't), that relates to a USART connected to interrupts on something like an ATMega, so it wouldn't really load the SPI I guess, by some clever design. Yes I know, printing is never really for free. Why is debug_printf (lib_logging) is a LOT lighter weight for real time printing? Does the debug usart enter the debug core, and floats over to XTAG3? Or is there the standard formatting that takes cycles here? When will debug print delay the SPI bus? That being said, when I did remove the debug (as seen above) loading of the SPI_CLK
it still stopped. Ok that it one can see trace of prints in the crash call stack, but does that prove that this is the
cause? An SPI bus that doesn't work will let the WiFi card rather alone, but shouldn't halt the XCORE, really? Or is it just the result? There is no debug prints in spi_master in any case. But as long as spi_master is not a task with its own core I guess you have a point. I have a feeling that the design here is not optimal.
ASIDE right now:
I see that when it "just hangs" with no crash error in the console, I now do see crash info in the Debug window, with stack trace like. By the way, this is with a different WiFi board. Same behaviour. First the log:
Code: Select all
[ 582 ms] **WELCOME TO THE SIMPLE WEBSERVER DEMO**
[ 634 ms] Switching on Wi-Fi module....
[ 687 ms] init
[ 1791 ms] WriteN 1 10
[ 2463 ms] read2 1 ff.ff
..missing this:
Code: Select all
xrun: Program received signal ET_ILLEGAL_PC, Illegal program counter.
[Switching to tile[0] core[2]]
0xffffffff in ?? ()
..then the Debug stack:
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_app_tiwisl_simple_webserver.xe [xCORE Application]
xCORE Debugger (10:18 21.09.17) (Suspended)
tile[0] core[0] (Suspended)
2 wifi_led_server() wifi_led_server.xc:29 0x00041718
1 xhttpd() xhttpd.xc:58 0x000412ad
tile[0] core[1] (Suspended)
3 xtcp_wifi_on() xtcp_client.xc:64 0x0004156c
2 xhttpd() xhttpd.xc:65 0x000412ec
1 __main__main_tile_0_task_wifi_led_server_2() main.xc:43 0x000412a1
tile[0] core[2] (Suspended: Signal 'ET_ILLEGAL_PC' received. Description: Illegal program counter.)
11 <symbol is not available> 0xffffffff
10 __sfvwrite() 0x000449ce
9 __sprint() 0x00044464
8 vfiprintf() 0x00044038
7 iprintf() 0x0004281a
6 wifi_tiwisl_spi_read() wifi_tiwisl_spi.xc:127 0x0004201e
5 read_and_wait_for_event() wifi_tiwisl_server.xc:167 0x00041dac
4 write_and_wait_for_event() wifi_tiwisl_server.xc:144 0x00041d44
3 wifi_tiwisl_server() wifi_tiwisl_server.xc:305 0x0004194e
2 __main__main_tile_0_task_xhttpd_1() main.xc:42 0x0004128d
1 __start_core() 0x00044564
tile[1] core[0] (Suspended)
2 _done() 0x00040440
1 _done() 0x0004043e
xgdb (10:18 21.09.17)
/Users/teig/workspace/_app_tiwisl_simple_webserver/bin/_app_tiwisl_simple_webserver.xe (10:18 21.09.17)
..or maybe this is just because I by coincidence was doung Debug instead of Run? I tested this, and it's probably so. When it "hangs" after this:
Code: Select all
[ 564 ms] **WELCOME TO THE SIMPLE WEBSERVER DEMO**
when run as Debug it shows this with SPI_CLK connected and nothing if I do Run:
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_app_tiwisl_simple_webserver.xe [xCORE Application]
xCORE Debugger (10:48 21.09.17)
tile[0] core[0] (Running)CDTDebugModelPresentation.12=signal
tile[1] core[0] (Running)CDTDebugModelPresentation.12=signal
xgdb (10:48 21.09.17)
/Users/teig/workspace/_app_tiwisl_simple_webserver/bin/_app_tiwisl_simple_webserver.xe (10:48 21.09.17)
