DIY evaluation board with XE216-512-TQ512

[eez-open]

After few days of studying xCORE I decide to definitely give it a try as my next MCU platform that should goes way beyond currently used Arduino Due (32-bit), and give enough flexibility and performance that going into FPGA waters could not be just postponed, but completely unnecessary. My background in electronic is pretty basic, but I have a lots of time on disposal to invest in this adventure, and hopefully with your assistance it will be completed successfully.
As first step I tried to make a compilation of pins assigned to the following slice card and on-chip capability:

• LCD sliceCARD
• SDRAM sliceCARD
• USB (XE216 on-chip)
• Ethernet (XE216 on-chip)

For Ethernet pin mappings xCORE-200 eXplorerKIT board is used that also feature XE216-512-TQ512 MCU that I'd like to use on my evaluation board. Why that MCU? Because it has the highest pin count and do not come in BGA package that is from my perspective, and I believe many other DIYers, not convenient at all since require more skills, equipments and higher budget.
I made a table based on existing XMOS document and match LCD sliceCARD with Triangle slice slot pin mapping, and SDRAM with Star slice slot pin mapping. That also mean that LCD can address only 16-bit RGB color space (despite 24-pin bus available on display), use I2C for touchscreen controller, and that SDRAM address and data buses are multiplexed. Additionally, I presume that flash will be connected only during boot time (via QSPI). You can see columns that I've added on the right where far right column (Available) shows what is left when above mentioned hardware but also software libraries are in place:



The end result is not so encouraging, four pins that left barely could be used for one SPI channel. There is a slight chance that I misinterpret usage of USB library on this MCU and that X1D02 thru X1D09 (8 pins) are available (your input is welcome here). If not, that I have to rethink about such a "full Monty" approach and try to cut the corners or try to optimize pin usage. Regarding pin usage optimization I presume that only display addressing could be further shrink down if e.g. 16-bit parallel bus (5-6-5) is replaced with serial one using three 8-bit daisy chained shift registers. Clock frequency of 4.3" display that I'd like to use is not so high (typ 6.5 MHz) therefore clocking shift registers with three times higher frequency should be doable with xCORE. In case of serial communication, a full 24-bit RGB (8-8-8) can be deployed and pin count will drop down from 16 to 2 (clk + "strobe") and increasing total number of available pins to 20 for GPIO and few other peripherals, that I'd like to add on this evaluation board.

Thanks in advance for your comments and suggestions.

[eez-open]

Hm, serial interface for daisy chained 8-bit shift registers will require three instead of mentioned two pins (i.e. CLK, DATA, LATCH/STROBE) and its clock frequency probably should be much higher then what I said before. I have to investigate that further and for beginning find out what screen refresh rate is optimal.

EDIT: 2-wire xCONNECT Link to the xSYS header pins are wrongly assigned in the table from previous post. It should be X0D40 ... X0D43 instead of X0D39 ... X0D42.

[eez-open]

This is a working draft of my evaluation board on which I've connected XE216-512-TQ128 to the following peripherals:

• TFT 4.3" LCD with touchscreen controller
• SDRAM
• Flash (used only during boot)
• USB host/device OTG
• 10/100 Mbit full/half duplex Ethernet
• Audio output (with small amplifier)
• EEPROM
• Micro SD Card
• RTC with supercap backup
• Programmable LED x 3, 2 x optoisolated outputs and 2 x optoisolated inputs
• Optional connector for cheap W5500 Ethernet module
• Optional connector for Riverdi 20-pin LCD with controller

The evaluation board schematic is based on not-confirmed presumption that USB and Ethernet consume almost everything on Tile 1. On the other side (or tile) adding SDRAM and LCD did the same on Tile 0. Therefore if I'd like to preserve possibility to evaluate native USB and Ethernet functionality of the xCORE and still have few more pins to control other peripherals I decide to "optimize" LCD interface. I'm not sure if that is going to work, here is why: if parallel access is used as on LCD sliceCARD, data should be send with clock frequency of e.g. 8 MHz. My optimization means that parallel screen data is serialize and that require 24x or 16x faster clock. Even with 16-bit color space it is 128 MHz. I don't know if MCU can generate data stream with that speed on selected 1-bit port. If we pretend that is possible then the schematic that follows could make sense.
Before that here is update pin mappings:





The LCD is connected using 40-pin 0.5 mm connector. That pinout is more or less standardized among 4.3" (480x282) displays. The only difference that I have spotted is DE (Data enabled) signal. As touch controller a cheap AR1021 is selected. WLED backlit supply is based on TPS61169 that comes with PWM input for dimming, too. 3.3 V and 1 V are derived from stabilized DC input (5-16 V) using two sequenced TPS61208 buck converters. Sequencing is controlled by TPS3808G33 who is monitoring 3.3 V rail.
LCD data serialization is achieved with two 74VHC595 8-bit hi speed shift registers. Color encoding is 5-6-5 (RGB), and unused LSB bits are grounded.



SDRAM interface is based on reference design. On this sheet we can also found reset generator made with TPS3808G09 that monitor 1 V rail, for automatic reset. The manual reset is also possible using SW1. Flash is attached to the MCU only during boot procedure. Six pins predefined for QSPI are after that available for SDRAM interface. The LATCH signal (X0D00) will be also available after the boot.



Here we have USB that should be both device and host according to OTG (on-the-go specifications). Due to that another power supply is added to provide 5 V (up to 700 mA) when USB act as host. This section is still nebulous since I didn't find any reference in MCU datasheet regarding OTG operations. All what I found so far is that USB_ID should be left open.
MCU clock is generated by xtal oscillator, and XSYS connector is connected to JTAG and 2-wire xlink.



16 pins on Tile 1 are left unconnected (due to USB and Ethernet lib usage). Other pins are mostly consumed by Ethernet PHY. This part of design is based on work of Bianco presented here.
I didn't use another oscillator for generating 25 MHz, but only xtal that should be fine according to datasheet. It's shame that I cannot simply use Si5351, due to its first-time programming "issue". CDCE913 is another option, but it's rather expensive.



Finally, here we have few other SPI peripherals: EEPROM, micro SD Card, RTC, I/O expander and optional W5500 Ethernet. They are all connected to the same SPI channel (SPI1) and to "chip select" pin counts is optimized using another 8-bit shift register (IC24). Therefore for accessing target peripherals one need to set its CS signal first. That can be done with max. speed, so CS procedure shouldn't affect access speed too much.
There is also another SPI channel (SPI2) that is connected to Riverdi LCD only.

Thanks in advance for your comments and suggestions (PDF are also attached for easier review).

[eez-open]

I made a few small corrections to the above design:

• Power input diode (D2) is replaced with p-ch mosfet
• LED1 was wrongly biased
• IC6 RESET output missed pull-up resistor, one is added connected to +3V3
• Card detect is added for SD card
• 25 MHz xtal (Y1) is replaced with oscillator

[eez-open]

I've finished a first version of the PCB for this project. PCB is 4-layer, the simplest one (only thru-hole vias) with dimension 100 x 85 mm that is within limits of cheap Chinese prototyping manufacturers. Top and bottom layers rendered with OSHpark are shown below (inner layers were used for GND and power). On the bottom side are placed only micro SD card socket (J2) and optional 20-pin Riverdi LCD socket (X5). Passive components are rather large: 0805 and 0603 but it should be easier to works with them. When design become completed I'll publish all files (PCB files, Gerbers, BOM) on the GitHub.

[eez-open]

I've added some more options in the latest revision that are optional but adds more flexibility and resilience against ESD:

• Two 4-line ESD protection ICs (TPD4E001DRLR) are added on MCU pins that are exposed via XSYS 20-pin connector i.e. JTAG and 2-wire xlink0. Total number of lines that should be protected are nine, not eight, and TRST_N is not wired to ESD protection, but that MCU input is to some extend protected with 74LVC1G07SE-7
• Boot mode selection is added. Therefore one could choose between QSPI (000) and slave SPI mode (010)

[mon2]

Have you considered the XMOS created part that is stock from Digikey? This variation of the Si5351A PLL is factory programmed to offer 3 output clocks including 24 Mhz. You will need to review that if you do alter any of the clocks during runtime over I2C interface that the CPU clock (if driven by this PLL) is not interrupted else you will have a potential crash.

https://www.silabs.com/internal-apps-ma ... dendum.pdf

offers the details of the clock upon power up. Used on some XMOS boards.

https://www.digikey.com/product-detail/ ... ND/5799560

[eez-open]

Thanks, that looks promising, but I think that I can live in this moment with two XCO that cost me a little bit above 0.8 € on qty of 2. I've checked so far all physical dimensions of all components that needs to be created in Eagle, and only MCU is missing, but its on the way from Farnell, I expect it next week. I bought two XTAG, too. I made also few corrections on PCB, e.g. micro SD Card socket was rotated for 180 degrees :).

[mon2]

The most popular footprint for oscillators is the 3225 footprint. Such parts are typically under $ 0.40 USD in 1k qty on T&R from Asia. Source: WTL (Shenzhen, CN).

Can share some more comments after our lunch...

[SpacedCowboy]

I don't suppose you have an updated schematic do you ? There's a lot I'd like to (ahem) lift from this :)

Cheers
Simon