Higher speedgrades coming?

[ozel]

I noticed in the XVF3000 datasheets that those are coming at a higher speed grade than usual (12) and thus run at 600 MHz per tile by default.
Can we expect similar speed bumps in the xCore 200 series?

While at it, I'd love to see LVDS/SLVS capable I/O pins...

[Gothmag]

I'd love to see them scale from 1-n cores. 500/n mhz rather than 500/5+n. I haven't looked but does that mcu just allow 6 threads running at the 100mhz speed or is it still 5 with a bump to 120?

[ozel]

5 cores @ 120 and 6 @ 100 MHz
https://www.xmos.com/download/private/X ... 1.0%29.pdf

[infiniteimprobability]

Can we expect similar speed bumps in the xCore 200 series?

No plans currently. There is nothing to stop you buying the xvf3000 part though and using that at 600MHz, if you don't mind paying for the privilege of using the voice processing IP but not doing so.

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I'd love to see them scale from 1-n cores.

Due to the 5 stage pipeline and the logic, which was able to be simplified (made faster) by removing operand forwarding because only one stage of a thread is being executed at one time, the restriction of f/5 maximum was introduced. The chip is designed to be running a number of threads (aka logical cores) concurrently. Interestingly, the XS1 family has a 4 stage pipeline so f/4 can be achieved. XS2 needed an extra stage to get the performance up while adding the extra logic of dual issue and new instructions.