Hello everyone.
I want to ask if there is the possibility to add more than 1 spdif_tx channel on the MC Audio Evaluation Platform (software-wise).
It is possible a strapping like the following:
For Outputs:
4 x Spdif channels (L+R) (1->8)
and
2 x I2S channels (L+R) (9->12)
For Inputs:
4 x I2S channels (L+R) (1->4)
Thank you in advance.
With best regards,
Chris.
About the XCORE-200 MC Audio Platform.
-
- New User
- Posts: 3
- Joined: Wed Jan 31, 2018 3:39 pm
-
Verified
- XCore Legend
- Posts: 1140
- Joined: Thu May 27, 2010 10:08 am
Hi yes, adding more SPDIF is possible. you will need to consider a few things though. SPDIF TX currently connects in to audio (i2s) on tile[0] and par's (forks) from there. Something like this maybe..I want to ask if there is the possibility to add more than 1 spdif_tx channel on the MC Audio Evaluation Platform (software-wise).
It is possible a strapping like the following:
For Outputs:
4 x Spdif channels (L+R) (1->8)
and
2 x I2S channels (L+R) (9->12)
For Inputs:
4 x I2S channels (L+R) (1->4)
Code: Select all
par
{
#if defined(SPDIF_TX) && (SPDIF_TX_TILE == AUDIO_IO_TILE)
{
set_thread_fast_mode_on();
SpdifTransmit(p_spdif_tx_0, c_spdif_out[0]);
}
{
set_thread_fast_mode_on();
SpdifTransmit(p_spdif_tx_1, c_spdif_out[1]);
}
#endif
Code: Select all
outuint(c_spd_out[0], samplesOut[SPDIF_TX_INDEX]); /* Forward sample to S/PDIF Tx thread */
outuint(c_spd_out[0], samplesOut[SPDIF_TX_INDEX + 1]);
outuint(c_spd_out[1], samplesOut[SPDIF_TX_INDEX + 2]);
outuint(c_spd_out[1], samplesOut[SPDIF_TX_INDEX + 3]);
So adding another SPDIF can be done just by modifying audio.xc. Probably easiest to make c_spdif_out an array and pass it through to deliver.
There should be plenty of 1b ports available. Easiest would be to use the TOSLINK out port. You should have enough 1b ports left to do 4 channels as long as you are not using all 8ch in and out of SPDIF.
You should also have enough logical cores available for the basic builds too. I think there are only 2 cores used on Tile 0 so plenty left (6)
So a bit of fiddling in the code but all sounds feasible and should be low risk.
Do note however that we reclock the SPDIF to MCLK. This is to remove the 2ns pk-pk jitter from the output (port IO is synched to the core clock). I recall that it technically just fits inside the jitter mask but resynch is a good idea for open systems.
Engineer at XMOS
-
- New User
- Posts: 3
- Joined: Wed Jan 31, 2018 3:39 pm
Hello again infiniteimprobability,
Finally I manged to create the firmware with the spdifs.
The following straping: For ins 4xI2s and for outs 10xSpdif and 2xI2s is working up to 192kHz with out problem.
I just changed the parts that you have mentioned above plus the following:
void SpdifTransmitPortConfig(out buffered port:32 p, clock cl, in port p_mclk);
to
void SpdifTransmitPortConfig(out buffered port:32 p[5], clock cl, in port p_mclk); Now the 5 Spdif ports be clocked by clock block.
Thanks for all the help.
With best regards,
Christos.
Finally I manged to create the firmware with the spdifs.
The following straping: For ins 4xI2s and for outs 10xSpdif and 2xI2s is working up to 192kHz with out problem.
I just changed the parts that you have mentioned above plus the following:
void SpdifTransmitPortConfig(out buffered port:32 p, clock cl, in port p_mclk);
to
void SpdifTransmitPortConfig(out buffered port:32 p[5], clock cl, in port p_mclk); Now the 5 Spdif ports be clocked by clock block.
Thanks for all the help.
With best regards,
Christos.
-
Verified
- XCore Legend
- Posts: 1140
- Joined: Thu May 27, 2010 10:08 am
Good stuff! Thanks for feeding this back.Finally I manged to create the firmware with the spdifs.
Engineer at XMOS