xCORE and Side-Channel Attack

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aclassifier
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xCORE and Side-Channel Attack

Post by aclassifier »

I have been made aware of something called Side-Channel Attack (SCA). It seems to be either Simple Power Analysis (SPA) or Differential power analysis (DPA) (Power analysis). I have started blogging a little about it [1].

I am sure many of the users here would know this already. However, I will write a short intro for the novices, like myself:

The theme is about finding out what a device does when it solves some cryptographic problem, in order to crack some key, etc. Toolsets are being sold, with capture boards and target/victim boards. There is no xCORE target board out there. I have queried some about this at a forum [2], where I also have mentioned xCORE.

In [1] ("XMOS") I have also quoted some very recent marketing material from XMOS where they talk about xcore.ai. Reading between the lines there I think I see that XMOS is aware of side-channel attacks. They also mention a random generator on xcore.ai.

I would think that it would be easier to obfuscate cryptographic calculations (as listened to over a radio or on the power line) on the xCORE architecture than on any other architecture I would know of. Multiplexing tasks on same logical core with [[combinable]] (how random could that be done?) and on different cores (how random and obfuscating could what's being done at the different core's scheduled cycles be?)

Any comments on this very interesting theme?

[1] Fault injection detection (standard disclaimer, no ads, no money, no gifts, just fun and expenses)
[2] Task/processes to insert random noise
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Øyvind Teig
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Post by Ross »

The uni XMOS was originally spun out of had an active crypto group that investigated these kind of attacks, they provided some interesting demos whilst I was there!
Technical Director @ XMOS. Opinions expressed are my own
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Post by aclassifier »

Interesting. At https://research-information.bris.ac.uk ... lications/ I still see 2 profiles, 2 research units, 29 research outputs and 4 not active projects.

But there is at leat one paper from 2022.

I just wondered whether the XMOS architecture contains any artefacts that would make them more or less resilient.

This is only of theoretical interest for me, though! I just happened to come across the theme some years ago.
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Øyvind Teig
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Post by Ross »

Oh I'm quite old now - things could have changed quite a bit :D
Technical Director @ XMOS. Opinions expressed are my own