Hello all,
I am extremely new to using the XMOS multicore microcontrollers and, as a result of the ongoing supply shortage, am trying to modify a design to make it support a wider range of ADC/DAC options; so here's the issue in question: can I use an XE216-512-TQ128 as a a sort of TDM demux? I have an ADAU1452 that is capable of streaming (up to) 16x 32 bit audio channels at (up to) 192kHz and I would like to have a flexible output stage that will allow me to support multiple DAC options. The original design featured an Asahi Kasei AK4458 DAC which would be directly connected to the ADAU and supports 8 channel TDM stream natively but other DAC options require demultiplexing and (ideally) I could use the XE216 for this function. It would also be pretty cool to have a few more channels as the DSP does technically support this.
Ideally, the XE216 would take as an input a 16 channel TDM stream @ 192kHz (MCLK, BCLK, LRCLK, TDM) and output multiple PCM (I2s) streams to multiple DACs like the ES9016s (MCLK1, BCLK1, LRCLK1, DATA1_1, DATA2_1, DATA3_1, DATA4_1, MCLK1, BCLK2, LRCLK2, DATA1_2, DATA2_2, DATA3_2, DATA4_2) - is this possible? I apologize that this is such a naive question, and I suspect that this is just a trivial modification to the i2s library but I found it difficult to follow. If anyone could point me in the right direction, I would be eternally grateful!
I have attached the TDM serial audio data format that the ADAU outputs, hopefully this helps!
XMOS as 16 channel TDM stream demux/I2S output
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XMOS as 16 channel TDM stream demux/I2S output
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The answer is yes you can do it. But it will take some work.
OK, just to clarify what you wrote. The ADAU1452 is capable of a BCLK up to 24.576 MHz which, at 192 kHz and 32 bits per sample, is only 4 channels per TDM lane. The only way you'll get 16 ch/frame at 32 bits per sample is at 24.576 MHz / 16 / 32 = 48 kHz. You're not going to get 16x32b samples per TDM lane at 192 kHz from that chip. The XE216 is well able to handle BCLK < 25 MHz so no worries there.
If you want to support lots of modes that will take more code to support 16, 8, or 4 channels per frame, and let the XMOS MCU what exact mode it should be operating in. And if you want to get 8 channels per frame at 192 kHz or 16 channels at 96 kHz you'll need to add support for 16 bit samples in addition to 32 bit samples. That's all obvious from the ADAU1452 spec. I wouldn't recommend 24 bit samples, anyway the ADAU1452 doesn't seem to support them without zero padding so it's kind of a non-issue, you treat 24 bit samples like 32 bit samples.
If you have fixed 16 ch/frame and 32 bits/sample I would stick to supporting up to 48 kHz at first. Then you need to use the port map spreadsheet (https://www.xmos.ai/file/xcore-200-devices-portmap/) to see if you can get enough 1 bit ports on a single tile to do the TDM->I2S conversion. I think you want to keep all TDM and I2S on the same tile if possible, otherwise put both TDM on one tile (this will run in a single core) and all I2S on the other (this should also run on a single core) and use a streaming channel to get the samples across. If you go to higher rates you might need two cores for the I2S output, not sure. That will raise the complexity a bit.
For the MCLKs I wouldn't generate it in the XMOS chip. If you can use your clean MCLK everywhere, maybe you need to fan it out, whatever, don't use the XMOS to divide it since it will be jittery. Most DACs should be able to work with 24.576 MHz MCLK or 12.288 MHz MCLK so you can probably use a single MCLK for everything.
The TDM will work as either master or slave to the ADAU1452 (master is a little simpler and would run slightly faster to give you more margin). You'll run the I2S in master mode.
OK, just to clarify what you wrote. The ADAU1452 is capable of a BCLK up to 24.576 MHz which, at 192 kHz and 32 bits per sample, is only 4 channels per TDM lane. The only way you'll get 16 ch/frame at 32 bits per sample is at 24.576 MHz / 16 / 32 = 48 kHz. You're not going to get 16x32b samples per TDM lane at 192 kHz from that chip. The XE216 is well able to handle BCLK < 25 MHz so no worries there.
If you want to support lots of modes that will take more code to support 16, 8, or 4 channels per frame, and let the XMOS MCU what exact mode it should be operating in. And if you want to get 8 channels per frame at 192 kHz or 16 channels at 96 kHz you'll need to add support for 16 bit samples in addition to 32 bit samples. That's all obvious from the ADAU1452 spec. I wouldn't recommend 24 bit samples, anyway the ADAU1452 doesn't seem to support them without zero padding so it's kind of a non-issue, you treat 24 bit samples like 32 bit samples.
If you have fixed 16 ch/frame and 32 bits/sample I would stick to supporting up to 48 kHz at first. Then you need to use the port map spreadsheet (https://www.xmos.ai/file/xcore-200-devices-portmap/) to see if you can get enough 1 bit ports on a single tile to do the TDM->I2S conversion. I think you want to keep all TDM and I2S on the same tile if possible, otherwise put both TDM on one tile (this will run in a single core) and all I2S on the other (this should also run on a single core) and use a streaming channel to get the samples across. If you go to higher rates you might need two cores for the I2S output, not sure. That will raise the complexity a bit.
For the MCLKs I wouldn't generate it in the XMOS chip. If you can use your clean MCLK everywhere, maybe you need to fan it out, whatever, don't use the XMOS to divide it since it will be jittery. Most DACs should be able to work with 24.576 MHz MCLK or 12.288 MHz MCLK so you can probably use a single MCLK for everything.
The TDM will work as either master or slave to the ADAU1452 (master is a little simpler and would run slightly faster to give you more margin). You'll run the I2S in master mode.