USB to I2S

[lmariotti]

Hi everyone, I've to develop a USB to I2S converter with XU208-128-QF48-C10, there's maybe any free-to-use code that already perform this task?

Thanks everyone.

[Ross]

The code here: https://www.xmos.ai/develop/usb-multichannel-audio/ can be easily modified to run on a single tile device

<moved to USB Audio>

[lmariotti]

Thanks for the fast reply and for the code provided.

I was looking at app_usb_aud_xk_evk_xu316 READ ME file:
"Supports for the following sample frequencies: 44.1, 48, 88.2, 96, 176.4, 192kHz"

My application should be able to sample until 768kHz, is the XU208-128-QF48-C10 capable to reach these requests? Or I should pick a different XMOS MCU?

[Ross]

We don't currently test anything over 192kHz since we have no dev kits that support it. We previously had kits that ran at 384kHz but these are no longer available.

Out of interest I did try on my lunch break by making the following changes:

Code: Select all

diff --git a/app_usb_aud_xk_316_mc/src/core/xua_conf.h b/app_usb_aud_xk_316_mc/src/core/xua_conf.h
index 8bc72af..4b4366b 100644
--- a/app_usb_aud_xk_316_mc/src/core/xua_conf.h
+++ b/app_usb_aud_xk_316_mc/src/core/xua_conf.h
@@ -114,12 +114,12 @@
 #endif
 
 #ifndef MCLK_48
-#define MCLK_48            (512*48000)   /* 48, 96 etc */
+#define MCLK_48            (512*48000*2)   /* 48, 96 etc */
 #endif
 
 /* Maximum frequency device runs at */
 #ifndef MAX_FREQ
-#define MAX_FREQ           (192000)
+#define MAX_FREQ           (192000*4)
 #endif
 

A couple of notes:
- 768KHz requires a 49MHz bit clock so at least a 49MHz MCLK. Setting the define MCLK_48 causes the Secondary/Application PLL settings to be adjusted to generate this frequency.
- The DACs on the new XK-AUDIO-316-MC board support 384KHz but the ADCs do not
- None of the hardware supports 768kHz but I eye-balled the I2S signalled on the scope and it looked fine
- I only tried on the 2channel input/2channel output build configuration with the xCORE as I2S master (2AMI2o2xxxxxxx)

Since this isn't something that we regression test then we cannot really officially support this configuration.

Good luck with your project!

[lmariotti]

Finally some times ago I went back to this project.

So far:

• MCU = XU208 with USB audio modified to run on single tile

• Modified MCLK_48, MCLK_44 and MAX_FREQ as you suggested;

• Added SI5351A for MCLK generator;

• Build: xmake --makefile=Makefile CONFIG=1AMi2o2xxxxxx;

Using 45MHz/49MHz MCLK everything works fine up to 384kHz.
Trying with 768kHz causes an error from foobar2000 Unrecoverable playback error: Audio device could not be initialized, that error remains until switch OFF and ON again.

I've checked I2S line, and it seems to be a bit "unstable" (e.g. in the following video there's LRCK)

With lower frequencies everyting is completely stable.

Any idea why this error message comes up? The same happens using TUSBaudio drivers and AISO interface.

[Ross]

I was running on an an XS3 based device that has a higher core clock. You could try over-clocking you XS2 based device.

(I assume *1*AMi2o2xxxxx is a mistake and you mean 2AMi2o2xxxxx)

[lmariotti]

Hi Ross, thanks for your reply,

you are correct, the build is 2AMi2o2xxxxx, mine was a typo.
With over-clocking do you mean hardware change the CPU main clock (aka 24MHz) or there's some software-way to do this?

[Ross]

In the xn file you can change the SystemFrequency. Operation isn't guaranteed, of course, but it might quickly show that this is (or is not) as timing issue - as I suspect it is.

Generally devices are sold at the following speed grades: xcore-200 (XS2 based): 500MHz, xcore.ai (XS3 based): 600MHz.

After re-reading you message I also see you are tying to run on a single tile device - my experiment was over two tiles so would have have more total MIPS available to it.

[lmariotti]

Hi Ross,

the overclock trick seems to do the job!
XU208 is running PCM up to 768kHz and both DSD Native & DoP up to 256!

Thanks for your support.

[HerbieSundiver]

Hi Ross,

I'd need your advice on a very similar topic: I need to implement 2AS12o2xxxxxdd - in both directions i.e. dsd-out and dsd-in to I2S with xmos being the I2S slave (MCLK is coming from our FPGA hardware), dsd up to 256 natively.
I tried the clock and SR increase with the XK-EVK-XU316 which is running fine
but now:
Please advise what is the best starting point or better where to change for the dsd-to-I2S input (ADC) side?
Would be cool to have dsd-in in the naming scheme but being a hardware guy I do not dare touching the "nice code" without asking :-)

Thanks so much in advance,
Sun