Generating master clock with Si5351A on XK-AUDIO-316-MC-AB board Topic is solved

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vladimir593
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Posts: 20
Joined: Tue Dec 12, 2023 11:33 pm

Generating master clock with Si5351A on XK-AUDIO-316-MC-AB board

Post by vladimir593 »

Hi everyone!

I tried to configure the onboard Si5351A-B-GT device via I2C on the XK-AUDIO-316-MC-AB board.
Unfortunately, it didn't work.
Earlier I used the following I2C config with the SI5351A-B04486-GT device on my custom XUF208 board:

i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, SI5351A_OE_CTRL, 0xF9);
// Enable Fanout of MS0 to other outputs.
i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, SI5351A_FANOUT_EN, 0xD0);
// Setup CLK2 output. Sets powered up, integer mode, src PLLB, not inverted, Sel MS0 as src for CLK2 o/p, 4mA drive strength)
i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, SI5351A_CLK2_CTRL, 0x69);
// Change R0 divider to divide by 2 instead of divide by 1. This stays at this value.
i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, SI5351A_MS0_R0_DIV, 0x10);
// Change R2 divider to divide by 8 instead of divide by 1. This will change depending on sample freq.
i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, SI5351A_MS2_R2_DIV, 0x30);
// Now we write the lower bits of Multisynth Parameter P2. This updates all the divider values into the Multisynth block.
// The other multisynth parameters are correct so no need to write them.
i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, SI5351A_MS0_P2_LOWER, 0x00);
// Wait a bit for Multisynth output to settle.
delay_milliseconds(1);
// Enable all the clock outputs now we've finished changing the settings. This will output 24.576MHz on CLK0 to xcore and 6.144MHz to DAC.
i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, SI5351A_OE_CTRL, 0xF8);
// Wait a bit for DAC to be ON
delay_milliseconds(1);

And it works. So, I assume that Si5351A-B-GT isn't preprogrammed like the SI5351A-B04486-GT device.
With the config mentioned above, I am getting 24.576MHz on CLK0 with the SI5351A-B04486-GT device
and 12.4997 Mhz with the Si5351A-B-GT device. Have anyone any idea how to get the right master clock frequency with
Si5351A-B-GT device?

P.S. I know about the I2C MUX switch and I configured it also.

Best regards,
Vladimir
View Solution
vladimir593
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Posts: 20
Joined: Tue Dec 12, 2023 11:33 pm

Post by vladimir593 »

UPDATE:

I have the solution.
I used Clock Builder Pro to generate an array of registers and data values.
uint8_t si5351reg[43][2] = {
{ 0x02, 0x53 },{ 0x03, 0x00 },{ 0x04, 0x20 },{ 0x07, 0x00 },{ 0x0F, 0x00 },{ 0x10, 0x0D },{ 0x11, 0x8C },{ 0x12, 0x8C },
{ 0x13, 0x8C },{ 0x14, 0x8C },{ 0x15, 0x8C },{ 0x16, 0x8C },{ 0x17, 0x8C },{ 0x1A, 0x0C },{ 0x1B, 0x35 },{ 0x1C, 0x00 },
{ 0x1D, 0x0F },{ 0x1E, 0xF0 },{ 0x1F, 0x00 },{ 0x20, 0x09 },{ 0x21, 0x50 },{ 0x2A, 0x00 },{ 0x2B, 0x02 },{ 0x2C, 0x00 },
{ 0x2D, 0x10 },{ 0x2E, 0x40 },{ 0x2F, 0x00 },{ 0x30, 0x00 },{ 0x31, 0x00 },{ 0x5A, 0x00 },{ 0x5B, 0x00 },{ 0x95, 0x00 },{ 0x96, 0x00 },
{ 0x97, 0x00 },{ 0x98, 0x00 },{ 0x99, 0x00 },{ 0x9A, 0x00 },{ 0x9B, 0x00 },{ 0xA2, 0x00 },{ 0xA3, 0x00 },{ 0xA4, 0x00 },{ 0xA5, 0x00 },{ 0xB7, 0x92 }};
//i2c function
void i2c_write_reg(client interface i2c_master_if i2c, uint8_t device_addr, uint8_t reg, uint8_t data)
{
uint8_t a_data[2] = {reg, data};
size_t n;
i2c.write(device_addr, a_data, 2, n, 1);
}
//write all regs
for(int i = 0; i < 43;i++)
{
uint8_t reg = si5351reg[0];
uint8_t data = si5351reg[1];
delay_milliseconds(1);
i2c_write_reg(i_i2c[0], SI5351A_I2C_DEVICE_ADDR, reg, data);
delay_milliseconds(1);
}

This is an example of an i2c config to generate 24.576 MHz MCLK on the CLK0 pin of Si5351A-B-GT.

Best regards,
Vladimir
Audma_lm
Member
Posts: 11
Joined: Thu Oct 05, 2023 3:14 pm

Post by Audma_lm »

Hi,
I've used for my project this library (previously .c) modified to use .xc features. It works pretty fine maybe you can check it.

Best regards
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vladimir593
Member++
Posts: 20
Joined: Tue Dec 12, 2023 11:33 pm

Post by vladimir593 »

Hi,

Looks cool, thanks a lot

Best regards