Hi,
I followed this tutorial to change the LPDDR clock frequency. However, it's not clear to me what the max clock frequency is.
From the EVK board schematics I found the LPDDR part number, and from its datasheet I can see that the max clock frequency may be up to 200 MHz, but it looks like it depends on a given "speed grade -5/-6" variant (maybe an operational mode?) that I can't figure out from the datasheet.
Is the max LPDDR clock frequency supported 166 or 200 MHz on the xcore.ai EVK?
Setting max LPDDR clock frequency
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andy-aic
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ACascarino - XMOS
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Hi Andy,
Agreed that their datasheet is a little incomplete - I'd expect their packaging information to include what their model numbers actually mean!
I believe it to be the case that the penultimate character in the part number (in our case W94AD6KBHX5I, so 5) is the speed grade of the device. This would imply a 200 MHz LPDDR frequency (as per the Clock cycle time parameter with a CAS latency = 3 from page 54 of their datasheet), which is corroborated by listings on e.g. Digikey - compare this listing for the -5 grade stating it to be a 200 MHz part with this listing for the -6 grade stating it to be a 166 MHz part.
Kind regards,
Angel
Agreed that their datasheet is a little incomplete - I'd expect their packaging information to include what their model numbers actually mean!
I believe it to be the case that the penultimate character in the part number (in our case W94AD6KBHX5I, so 5) is the speed grade of the device. This would imply a 200 MHz LPDDR frequency (as per the Clock cycle time parameter with a CAS latency = 3 from page 54 of their datasheet), which is corroborated by listings on e.g. Digikey - compare this listing for the -5 grade stating it to be a 200 MHz part with this listing for the -6 grade stating it to be a 166 MHz part.
Kind regards,
Angel