I am a recently converted XC programmer working on an usb audio product.
As I am new to XMOS eco system, I made many mistakes on my custom board design. During debugging I found out that the i2c output signal have glitcches even on official xcore.ai evaluation board.
The glitches happen on the rising edge of the clock signal. Since they are rising edge and the amplitude is not high enough, they seem not causing actual communication problem, but they do appear to be a reliability concern. Does anyone else see this problem?
My guess is that the glitches happen around the time when XMOS code switching between Hi-Z and actively driven mode on the SDA line.
In addition, I saw a behavior that I don't know if that is the intention. When i2c clock frequency set to 10 kHz, I would expect a clock signal on SCL line at about 50% duty cycle, but rather I observed the duty cycle at 10% (equivalent to 100kHz clock). So, there seems to be a maximum time that the clock pulled down, regardless of frequency setting.
I observed this on sw_usb_audio v8.1, without any change to original code.
i2c output signal glitches ?
-
- Member
- Posts: 14
- Joined: Wed Sep 25, 2024 5:46 am
-
Verified
- Experienced Member
- Posts: 86
- Joined: Sun Dec 13, 2009 1:12 am
Suspect you are referring to the short pulses on SDA at the start of the 9th bit time. This is completely normal and is the short period of time after the I2C Master (XMOS device in this case) has released the SDA line but before the I2C Target has driven the line low to indicate acknowledge. In this period nothing is driving the bus so it will start to be pulled high by the bus pullup.
These pulses have no consequence as nothing is sampling the bus in this time.
I2C SCL line isn't a traditional clock so there are no requirements for it to be 50% duty cycle, as long as all the timing parameters of the I2C spec are met then any duty cycle clock can be used.
Cheers,
Joe
These pulses have no consequence as nothing is sampling the bus in this time.
I2C SCL line isn't a traditional clock so there are no requirements for it to be 50% duty cycle, as long as all the timing parameters of the I2C spec are met then any duty cycle clock can be used.
Cheers,
Joe
XMOS hardware grey beard.