Hi,all
According their datasheet, why the 2b link bandwidth(stieaming) of the xu208-128-64 is 100MBit/s and the XS1-U6A-64-FB96 is 125MBit/s , and they are all the same 7.5ns symbol time ? I think that they should have the same performance. I hope somebody can explain this.
Thanks.
xConnect Link Performance
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I may be wrong, but as I recall, the XS1 series I/O pins can operate up to 100mhz whereas the xcore-200 series pins only go up to 60mhz.
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Hi tanlytam & bzyzny,
The links and pins are identical between XS1 and XCORE200.
Link speed depends on (a) your core clock frequency and (b) the speed at which your PCB traces can run.
At 400 MHz with 3 clocks spacing and 2 wires you end up transmitting 8 bits every 10 transitions is 10 * 3 * 2.5 = 75 ns
You may get away with 2 clocks spacing at 400 MHz (5 ns = 200 Mbits/s).
At 500 MHz you will need at least 3 clocks (6 ns = 167 Mbits/s).
The higher capacitance your traces are, the more variation you will get, the more clocks you will need.
Cheers,
Henk
The links and pins are identical between XS1 and XCORE200.
Link speed depends on (a) your core clock frequency and (b) the speed at which your PCB traces can run.
At 400 MHz with 3 clocks spacing and 2 wires you end up transmitting 8 bits every 10 transitions is 10 * 3 * 2.5 = 75 ns
You may get away with 2 clocks spacing at 400 MHz (5 ns = 200 Mbits/s).
At 500 MHz you will need at least 3 clocks (6 ns = 167 Mbits/s).
The higher capacitance your traces are, the more variation you will get, the more clocks you will need.
Cheers,
Henk
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Thanks henk, good explanation. I think part of the answer is also that the 7.5ns figure is the delay between symbols, therefore when running the tile core at 400mhz vs 500mhz, the duration of the symbol itself is different. I'm still a beginner with this stuff so I may be wrong again :)
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Ye s- there is a gap between symbols. To be able to distinguish symbols on the other side, this gap needs to be big enough.
The confusion is - this gap is measured in core-clocks - that are 2 ns (at 500 MHz) or 2.5 ns (at 400 MHz); since that is the only clock that is fast enough.
So we can have 2 or 3 clocks spacing, creating 4, 5, 6, or 7.5 ns space between symbols, depending on the clock rate.
The best approach is backwards - how much time do you need, what clock cycle time do you have, then divide the two to work out how many clocks you need between symbols.
Finally - the only difference between 2-wire and 5-wire is the number of bits transferred per edge. 2-wire transmits 0.8 bits per edge (8 bits plus one control bit plus one parity bit every 10 edges); 5-wire transmits 2 bits every edge.
Cheers,
Henk
The confusion is - this gap is measured in core-clocks - that are 2 ns (at 500 MHz) or 2.5 ns (at 400 MHz); since that is the only clock that is fast enough.
So we can have 2 or 3 clocks spacing, creating 4, 5, 6, or 7.5 ns space between symbols, depending on the clock rate.
The best approach is backwards - how much time do you need, what clock cycle time do you have, then divide the two to work out how many clocks you need between symbols.
Finally - the only difference between 2-wire and 5-wire is the number of bits transferred per edge. 2-wire transmits 0.8 bits per edge (8 bits plus one control bit plus one parity bit every 10 edges); 5-wire transmits 2 bits every edge.
Cheers,
Henk
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Hi, bzyzny and henk, thank you for your reply.
I mean that if the xConnect link of XS1 and XCORE200 are all using 2 wires and 7.5ns symbol time,they should have the same link speed. Am I right?
I mean that if the xConnect link of XS1 and XCORE200 are all using 2 wires and 7.5ns symbol time,they should have the same link speed. Am I right?
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Unfortunately its not that simple. To clarify, 7.5ns is the time between each symbol sent over the xconnect link. However, the clock rate of the main tile core determines the duration of the signal used to send an xlink symbol (which is a single byte plus a parity bit plus a control bit, so 10 bits total). In other words, an xmos chip running at 400mhz core clock has to wait the same amount of time, 7.5ns between each bit it sends on the 2b link, as an xmos chip running at 500mhz. However, the 500mhz chip can send each symbol 25% faster than the 400mhz chip. 500 divided by 400 is 1.25, so if 400 MHz gives you 100mbit/s then 500mhz gives 125mbit/s. Hope that helps, if not, then I suggest you read some books or tutorials on data communications.
Or am I missing your point? Are you trying to make an xs1 link to an xcore200? If so then I assume they would communicate at the lowest common speed, 100mbit/s
Or am I missing your point? Are you trying to make an xs1 link to an xcore200? If so then I assume they would communicate at the lowest common speed, 100mbit/s
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Thanks bzyzny.
To use the 7.5ns symbol time, I think that they all use the 400MHz system clock. because 1/400MHz = 2.5ns , 2.5ns * 3 = 7.5ns . Link configuration registers 0x80..0x88 can be used to get 7.5ns symbol time.
To use the 7.5ns symbol time, I think that they all use the 400MHz system clock. because 1/400MHz = 2.5ns , 2.5ns * 3 = 7.5ns . Link configuration registers 0x80..0x88 can be used to get 7.5ns symbol time.