Slicekit Modular Development System Is On Its Way

[dan]

Hello Everyone,

I have just updated the github hw_slicekit_system repo to reflect current progress since last time we discussed this.

https://github.com/xcore/hw_slicekit_system

Design of core boards and initial slicecards is under way - you can find all the details in the docs at the repo including overview, schematics and hw spec.

Please take a look and let us know what you think - there is still time/scope for changes where we have missed a cool feature or something. Ideas for slices also very welcome.

Pricing details and roll out schedule (and some pictures) will be forthcoming before long.

[DanB]

Hi Dan,

I was incredibly pleased to read that the SliceKit system is on its way! :) I had every good intention to get into XMOS last year but things, unfortunately, did not work out. I promised myself that I'd make amends this year and I'm plodding through the XMOS XS1 architecture and programming XC guides and really hoping to get some use out of my XC-1A and XK-1A development kits... The more I read the more XMOS excite me and I remember reading as discussions of the SliceKit system developed last year - Your recent update does not disappoint! I'd love to get hold of it; certainly it seems pretty good timing to be getting stuck into XMOS :).

I've read the associated documentation on Git a few times now. I've got a few questions/comments:

From my understanding SKT 0_0, SKT 0_1, SKT 1_0 and SKT 1_1 can be used to attach slices but PLG 0_0 can only be used to link core boards (by means of connecting PLG 0_0 of the slave board to SKT 1_0 of the master board). This explains why the outputs on PLG 0_0 and SKT 0_0 are the same (with the exception of XLA) as only one can be used - Either for a slice board or core board.

Assuming this understanding is correct:

1) On the Git overview it says: "To link two core boards together, the *connector 0* teeth can be plugged into the connector 0 slot on another baseboard, giving two 5b links between the two core boards along with the full complement of JTAG signals." Should this read "To link two core boards together, the *plug 0* teeth can be plugged into the connector 0 slot on another baseboard, giving two 5b links between the two core boards along with the full complement of JTAG signals."? It is possible that I am being pedantic and that "connector" can refer to a "socket" or "plug"... However, just checking!

2) Similarly, in the 'SliceKit hardware specification' document it reads: "PRSNT is used on PLUG_00 to detect it is plugged into SOCKET_10 of another core board. This signal is used to switch JTAG and CLK sources. Similarly, PRSNT_N is used on SOCKET_00 to detect another core board is connected." In this case, does SOCKET_00 refer to SOCKET_10? I think this is an example which does matter as '3.8 Connector pinouts' seems to show PRSNT_N on SOCKET_10 (presumably to contact GND on PLUG_00).

In summary, assuming my understanding is correct (the reason for clarifying the two above points which would otherwise be obvious), the only way to connect core boards is via PLG 0_0 and SKT 1_0, as in the diagram below. Is this correct? If so, from what I can understand connections between core boards may only result in a linear XS1 network. Is it possible to create other network topologies using the boards? For example, if I wished to implement a ring network? Will XMOS be developing any interconnect card/cable which allows this?



My only concern if the above image is correct is that it means the surface/desk/bench space required for the kit grows quickly with additional core board requirements. I appreciate, though, that this is a restriction that has had to be imposed to both breakout all of the signals in a convenient way whilst physically restricting people from connecting core cards in incompatible ways. It would be great if this could expanded (some how?) to stop slices that require a connector type 1 from being physically inserted into a connector type 0. (I did a have a think about how this could be done and could not think of an elegant solution).

Some other interests I have (and understand answers will be provided shortly) include:

A) Price? (Core board, slice boards).

B) Following from (A), will be a 'package' be available including a core board (or >1 core board, for core experimentation) and some/all slice boards?

C) Will all slices always be available to purchase? My assumption from the documentation is that the specification has been designed to allow easy home fabrication, however for those not that way inclined it would be highly beneficial to be able to purchase developed slice boards.

And lastly, but equally important, I particularly appreciate the fact that all XCore IO will be broken out onto a row of 0.1 inch headers! This is something I really missed (out of the box) on the XC-1A... It almost assumed (in fairness, a reasonable assumption) that anybody using the board would be proficient with a soldering iron to affix their own... The inclusion of the headers allows people to actually interface the processor to other devices, with less effort, out of the box in a temporary (think prototype) way.

Finally, I'd like to summarise that I am very excited by the proposals outlined. I think they will offer what many 'beginners' have wanted from XMOS for a long time - Finally a way to develop applications with a number of IO devices without having to concern oneself with hardware ability. Slices solve this inherently, with a flexible system that enables the developer to quickly 'plug' a prototype together with the requisite IO and get working on the nuts and bolts in software... It seems like an excellent way to prototype! It is, of course, also a fantastic way to demonstrate the inherent flexibility (and expandability) of the XMOS devices... The way in which projects can be scaled with the XMOS architecture would provide a great way for designs prototyped with the SliceKit to be expanded into a custom fabrication.

I, for one, am genuinely excited to get hold of the SliceKit. Great work guys! :)

Dan.

[DanB]

Oh, and Dan, a little off topic but whilst I've got the attention of the right man (I think!)... The XS1 DIP Module (as discussed here) - Any chance you could get these sent out into production? Please! ;)

[dan]

Hello Dan,

Thanks for the feedback - and enthusiasm! I've addressed some of your feedback below.

Hi Dan,
Assuming this understanding is correct:

1) On the Git overview it says: "To link two core boards together, the *connector 0* teeth can be plugged into the connector 0 slot on another baseboard, giving two 5b links between the two core boards along with the full complement of JTAG signals." Should this read "To link two core boards together, the *plug 0* teeth can be plugged into the connector 0 slot on another baseboard, giving two 5b links between the two core boards along with the full complement of JTAG signals."? It is possible that I am being pedantic and that "connector" can refer to a "socket" or "plug"... However, just checking!

Your understanding is correct. It should read as you put it above, I'll update the docs accordingly.

2) Similarly, in the 'SliceKit hardware specification' document it reads: "PRSNT is used on PLUG_00 to detect it is plugged into SOCKET_10 of another core board. This signal is used to switch JTAG and CLK sources. Similarly, PRSNT_N is used on SOCKET_00 to detect another core board is connected." In this case, does SOCKET_00 refer to SOCKET_10? I think this is an example which does matter as '3.8 Connector pinouts' seems to show PRSNT_N on SOCKET_10 (presumably to contact GND on PLUG_00).

In summary, assuming my understanding is correct (the reason for clarifying the two above points which would otherwise be obvious), the only way to connect core boards is via PLG 0_0 and SKT 1_0, as in the diagram below. Is this correct? If so, from what I can understand connections between core boards may only result in a linear XS1 network. Is it possible to create other network topologies using the boards? For example, if I wished to implement a ring network? Will XMOS be developing any interconnect card/cable which allows this?

I didn't write the HW spec so I'll have to double check but you are correct that boards can only be chained as per your diagram, if you use the slots/plugs directly. However in theory any 00 socket has suitable IO to connect to any other 00 socket. So we could for example make a slicecard that plugs into socket 00 and/or socket 10 with lvds buffers for xlinks. You could then use wires to interconnect the boards rather than the socket_10-to-plug-00 method. Using this approach you could make arbitrary network topologies. You could also arrange to create a housing in which the boards are stacked vertically using wires for xlinks.

It would be great if this could expanded (some how?) to stop slices that require a connector type 1 from being physically inserted into a connector type 0. (I did a have a think about how this could be done and could not think of an elegant solution).

Well slices that fit in socket 1 won't cause damage or anything if plugged into slot 0. However, I can see confusion might arise if you didn't realise a slice was compatible with socket 1 only and plugged it into a socket 0 and then tried to debug it. We plan on including some kind of icons or something silk-screened on the slices which denote their compatibility.

Some other interests I have (and understand answers will be provided shortly) include:

a) Details will be forthcoming nearer the summer, but the core board won't be expensive. Obviously slices depend on what's on them but basic connectivity like Ethernet, uarts etc won't be expensive.

b) TBD. What do you think would work best?

c) I envisage a decent subset of slices covering popular functionality like ethernet, serial IO, audio etc that can be purchased online, plus hopefully many other slicecard designs in individual github repos which anyone who wants one could order one from PCB train and build it up themselves, or persuade the designer of the slice to do it for them.

And lastly, but equally important, I particularly appreciate the fact that all XCore IO will be broken out onto a row of 0.1 inch headers! This is something I really missed (out of the box) on the XC-1A... It almost assumed (in fairness, a reasonable assumption) that anybody using the board would be proficient with a soldering iron to affix their own... The inclusion of the headers allows people to actually interface the processor to other devices, with less effort, out of the box in a temporary (think prototype) way.

Yup, that's for debug but also, so you can wire up multi drop busses between multiple slices, and so you can create alternative cards and wiring to directly plug onto them.

Finally, I'd like to summarise that I am very excited by the proposals outlined. I think they will offer what many 'beginners' have wanted from XMOS for a long time - Finally a way to develop applications with a number of IO devices without having to concern oneself with hardware ability. Slices solve this inherently, with a flexible system that enables the developer to quickly 'plug' a prototype together with the requisite IO and get working on the nuts and bolts in software... It seems like an excellent way to prototype! It is, of course, also a fantastic way to demonstrate the inherent flexibility (and expandability) of the XMOS devices... The way in which projects can be scaled with the XMOS architecture would provide a great way for designs prototyped with the SliceKit to be expanded into a custom fabrication.

Great! This kit has an IO capability well in excess of our other kits to date except the XDK and it should make it possible to realise systems of significantly greater complexity and potential without too much hardware work or expense, as you point out. It is for example, the only kit you can attach a 16 bit SDRAM to, apart from the XDK (which is quite expensive). It is also a generic kit for L-series devices which fills a gap in terms of dev boards.

As for the 40-pin DIP, I'm afraid we don't have any plans for that right now - it'll need someone from the community to drive it.

[DanB]

Hi Dan,

Thanks for taking the time to compose such a comprehensive reply. It certainly sounds fantastic! :)

I do hope that it turns out slices are easily available 'premade' (be that from XMOS or, as you suggest, the slice designer). From my limited research I have always found the cost of producing a limited (one or two off) run is prohibitive. Add on purchasing small component counts to populate the small number of PCBs and you are faced with a significant outlay compared to ordering in relative bulk. (Indeed this is the very problem I have with the 40 pin DIP at present). It'd be great if slices could be purchased with one (or two) core board(s) - possibly both options - with a few slices, as a package. In addition, and I think it is important, all of the core boards/slices should be available individually too. I suppose, I guess, that this comes down to really items being sold separately but with a reduction if purchasing a 'set' at once, though this is probably more thought for the distributor rather than XMOS.

I think it's important that a number of slices are available from XMOS to get people started. I can imagine, though, that given time it could be an interesting way for people to design their own and contribute to the hardware repositories (one of your reasons for the whole modular approach, I'm sure). Certainly from my point of view I can imagine designing a slice being an achievable stepping stone on the path towards a totally custom XMOS board. I'm really excited by the possibilities of the SliceKit... Really hoping the community get behind it! Hopefully something similar, in part, to the Ardiuno shield, etc... :)

[dan]

Hi DanB - that's kind of what we are planning, more or less.

Meanwhile, how about listing the kinds of slices and functionality you'd like to see in say, a 'Starter Set' and and 'Expansion Set'?

[daveg]

...arbitrary network topologies...

Whilst this should be possible, the current tools only support linear (line) and hypercube networks.
This does mean that you could have a "ring" of 2, as this is a line, or 4, as this is a valid hypercube, but no other sizes.

Any other network shape will cause the mapper to be unable to route the network.

It is planned to allow more network shapes and perhaps to allow user-specified routing, but these are not currently supported I'm afraid.


It *may* be possible to set up any additional links yourself after starting the network in a supported topology, but this will probably require changes to the routing which will be non-trivial to implement from a user program.

[DanB]

Dan,

I am unable to differentiate between a 'starter' and 'expansion' set because I think largely it suggests a particular slice is either more important or more difficult... And I think both of these vary depending on the application in mind. Despite this, some ideas include:

• Set A:
• 2x Core Boards
• 1x Bread Board (or should that be Bread Slice ;))
• 1x ADC/DAC Slice

I think that this set is particularly useful for people that already have a number of, say, sensors and other accessories (possibly used for other projects or with other hardware). Sometimes the biggest hurdle can be physically connecting everything together - Once that's done being able to use the devices may be relatively simple and will show where the XMOS architecture shines. Therefore, a slice which brings IO out on headers directly above a bread board, on the same slice, would be great. (I am aware the headers will already be available on the Core Board). This would allow people to learn how to work out pin numbering/naming and considerations regarding port widths, etc, too. Essentially, a genuinely useful way to (in my case) hook up anything in my box of sensors and get playing! (For example, sensors may interface with I2C, UART, SPI or anything else - This allows people to see how protocols are implemented 'the XMOS way', possibly introducing users to Git and collaborating on modules, etc, too). The ADC/DAC slice would be similarly useful, particularly in conjunction. Could have a pot on the slice fed from the 5V supply which can be used to input to the ADC. Similarly a row of LEDs on the outputs. Both of these (pot and LEDs) should be jumpered so if the user wishes to use the slice for an application (rather than an investigation) they can do so.

• Set B:
• 2x Core Boards
• 1x UART Slice
• 1x LCD Slice
• 1x Ethernet Slice
• 1x Keyboard Slice

These slices are based around the case studies in the 'Programming XC on XMOS Devices' document. I believe, based on the fact they were included, they are good candidates for demonstrating XMOS and also generally useful and interesting. I have added the 'Keyboard Slice' as I think this compliments the other slices nicely - Even a little 4x4 matrix keyboard would be cool and allow people to develop applications making use of the keyboard and display (basic games, for example).

Note that in both sets 2x Core Boards are suggested. This is simply because I think XMOS scaling is very cool and something like the Core Board is a good way to empower people to make use of that. (Particularly those that are not inclined to produce their own boards in order to try this).

Also, whilst writing this I can imagine a slice with either EEPROM or SD card slot would be nice. It's something which could be a great educational tool to 'learn' XMOS but also genuinely has application in individual projects - Exactly what the SliceKit is all about.

Of course, all of the slice flavours (that XMOS intend to sell) should be available to purchase individually, too! :)

Dave,

Thanks for the clarification. My interest in arbitrary network topologies was purely to understand the flexibility (and restrictions) of the SliceKit. I do not, at this time at any rate, have a requirement for any particular topologies... I can imagine it would be 'nice' to support arbitrary topologies in the future though! :)

[Berni]

This seams like a pretty nice idea indeed. It does have a slight problem with space when stacking them but yeah tha could be solved by making some sort of xlink cable adapter.

But i think the base set should include only 1 of the xcore boards as its a good idea to keep the cost down to not put off too many potential users by the price (They usually wont want to pay a lot for a MCU they dont know about much)

Another important thing is to include some adapter boards that bing the card edge connectors in to a standard 0.1in header so they can wire up there own stuff easily if they like (A 2 sided board with 0 components on it is cheep anyway)

So for a beginners kit i think it should include:
x1 Xcore base slice
x1 UI Board (A basic LCD along with some buttons and LEDs next to them)
x1 Breadboard area
x1 Interface board (Some ADC/DAC,5V level shifters,meaby a power mosfet output)
x1 SD card slot
x3 Card edge to 0.1in dual row header adapters

Then for the advanced kit all the stuff that comes with the beginners kit plus these:
x1 Xcore base slice (Yeah an extra one)
x1 PC Interface board (RS232, PS/2,VGA)
x1 Audio Interface (Multichannel audio,SPDIF,MIDI)
x1 Ethernet interface
x1 Wireless board (Some ISM band generic transceiver, self contained bluetooth chip,header for an xbee)

There are some other ideas i got that not sure where to fit them, meaby only having them available as extra upgrades:
-USB Host/Device interface
-High speed analog (Fast ADC,DAC for signal processing applications)
-SRAM memory

All these boards might take quite a while to design and get out, but the ones for the basic kit seam pretty straight forward.

[DanB]

Some great ideas Berni :) I think our general suggestions are pretty similar, however possibly grouped differently (though I had no intention of making an explicit beginner/advanced divide).

My only comments regarding your suggestions surrounds the 'Card edge to 0.1in dual row header adapters' - From the documentation, specifically slicekit_hardware_specification.pdf on Git:

3.7 Testpoints
Due to the edge card style of connectors used, it will be difficult to probe signals
of interest with an oscilloscope or logic analyser. For this reason each XCore IO
signal will be connected to a row of 0.1 inch headers next to the connector to which
those signals connect. This will probably be in the form of 2 rows of 12 header
pins or similar with additional grounds also. The signals connecting to each header
pin will be shown on the silkscreen for easy debug. This scheme also allows for
interconnection of signals on the core board should this be required for advanced or
development work (e.g. using a global I2C bus).

Do you still think that a Slice is required to breakout the IO, or would the headers on the Core Board be sufficient? I'd have thought the latter, though I can understand that perhaps a user may develop something based on the headers that they'd like to conveniently be able to remove and reattach at a later date (e.g., they may use a 'Breakout Slice' per project they are working on).

Either way, interesting to have read your opinions! :)