USB aud L1 ref design: master clock at 45MHz / 49MHz ??

[xcoreuser]

Hello,
a new question about the XS1 and the L1 reference design.
The board sold by Xmos comes with two oscillators at 24.576MHz and 11.2896MHz, used for sampling at 48KHz or 44.1KHz, respectively. In the "customdefines.h" file, this corresponds to the following settings:
#define MCLK_441 (256*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (512*48000) /* 48, 96 etc */

Our question is: Can we drive higher clock frequencies, namely 49.152MHz and 45,1584MHz, to the MCLK input pin, or are them *too high* for the the XS1 and L1 reference design to work properly?

We tried to use external oscillators with such frequency values, and of course we modified the "customdefines.h" settings as follows:
#define MCLK_441 (1024*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (1024*48000) /* 48, 96 etc */
but the board does not seem to work. Precisely, it is normally recognized by the USB host PC, but the audio signal received from the board is zero. Notice that we have already successfully used an external oscillator with the original frequency, and everything is fine in this case.

The two possible reasons for this behaviour are:
1) the frequency values are too high
2) the design is not fully parametrized in MCLK_441 and MCLK_48, and there are some frequency or division values hardcoded somewhere in the design.

Any hints?
Thank you veru much!

[lilltroll]

I have used clocks around 50 MHz on the XAI board. The port logic on the XCORE chips can handle MCLKS > 50 MHz, but you have to check the oversampling ratio, so the MCLK, BCLK, LR has the correct communication speed at this higher MCLK.
You can also check in the simulator that you have the correct waveform-pattern and that you are not starved out of time, e.g. the fact that the port logic can handle the speed is not the same as you have CPU time for all the needed instructions.

[Ross]

Are you sure the CODEC is set up correctly for these clocks? I suspect the board will need a mod.

[xcoreuser]

Ross, thank you for your reply. In fact, the Codec was physically removed from the board and an external I2S source was connected to the XS1 chip with the appropriate (higher frequency) clocks. So, our concern is that either
1) the frequency values are too high for the pin / for the XS1 design, or
2) the design is not fully parametrized in MCLK_441 and MCLK_48, and there are some frequency or division values hardcoded somewhere in the design.
Thank you!

[Ross]

Ross, thank you for your reply. In fact, the Codec was physically removed from the board and an external I2S source was connected to the XS1 chip with the appropriate (higher frequency) clocks. So, our concern is that either
1) the frequency values are too high for the pin / for the XS1 design, or
2) the design is not fully parametrized in MCLK_441 and MCLK_48, and there are some frequency or division values hardcoded somewhere in the design.
Thank you!

Neither of these should be the case (I assume you are still running stereo?)

When you say "I2S source", do you mean that the XCore is now I2S slave (rather than default master?)

[xcoreuser]

When you say "I2S source", do you mean that the XCore is now I2S slave (rather than default master?)

right, the XCore is being used as an I2S slave
(and yes, we are still running stereo)

[Ross]

Regarding i2s slave mode in the L1 reference design, did you see this thread?

https://www.xcore.com/forum/viewtopic.php?f=8&t=1889