Power headroom on the XC-3 ?

[SpacedCowboy]

I was wondering what headroom was available when using the power circuit from the XC-3 reference design ?

I want to use a XS1-G04B-FB144-C4 (mainly because of the i/o, the RAM and the far-more-friendly BGA package than the horrendous QFN XS1-L2). Thing is that I want to put an ADV212 on-board (which requires a max of 320mA, an ADV7181C which has a max of ~250mA, an FTDI USB chip which can sink 220mA, and finally a couple of smaller (10's of mA) parts. So I'm going to need another 1A (to give me some headroom :)

Looking at the Datasheet for the XS1-G04B-FB144-C4, it's not clear how much power is potentially being used, but it seems that the quiescent power usage for the chip is 120mA, and a "core" power dissipation is 1600mA (since P=IV, V=1.0v, and PD=1.6 watts). Is that per core, or per chip ? If it's per-core then the supply on the XC-3 is already woefully underpowered (providing only 1A if I'm reading the schematic correctly, an LTC3417 provides 1A on circuit 1 and 1.5A on circuit 2).

Hmm - it seems that may be per-chip. http://xmos.com is down, so I couldn't open technical note X7561, but google has a cache, and a typical high-use figure for the G4 seems to be ~1800mW. It's still not clear to me how much of this power is from the 1v line, and how much from the 3.3v line, but it seems to be in line with the power dissipation being per-chip rather than per-core.

So, assuming I'm right in the above (love some feedback :), it seems there's basically no headroom in the PSU circuit (in fact it may be a little underpowered for high usage), which presents me with a problem because I'm useless at the analogue side of things.

I did have a thought of how to do it in a way that *I* understood :) If I connect a 5A 3.3v supply and a 3A 1v supply to the analogue inputs of an AVR chip, so I can read when the power supplies are operational, and then use said AVR to switch on the 1v supply to the rest of the board via a solid-state relay only after both 3.3v and 1v are stable, would that work ?

What I'm trying to do is match the requirements in section 5.10 of the datasheet where VDD must ramp to final value in 10ms or less and IO_VDD must be at final value before VDD hits 0.4v. Doing it this way would be a bit more expensive but easier for simple minds like mine to grok :)

Cheers
Simon.