XS1-L1-USB-AUDIO-2.0 48pin board debug problems!!

[eladmmor]

hey All!
I have built an USB to SPDIF board based on the single channel reference design(RD).

The board is very similar to the RD (uses the 48-pin XS1-L1 instead of the 128-pin, different SPI flash- AT25DF021 and IC oscillators instead of the crystals in RD).
The board uses no DAC, and exports the encoded SPDIF signal to be analyzed externally.

The board is successfully generating all the needed voltages(5.0V, 3.3V, 1.8V and 1.0V), and also the 13MHz clock is being generated and measured.

For some reason, when I connect the XTAG interface in order to burn the flash binary, the XDE flash does not recognize the chip (In flash cong' device options it shows - "XMOS XTAG-2 connected to None").

I'm not sure how to continue the debug.

Please help!

Thanks in advance,
Elad

[Bianco]

What output does "xrun -l" give in the command prompt?

[eladmmor]

Available XMOS Devices
----------------------

ID Name Adapter ID Devices
-- ---- ---------- -------
0 XMOS XTAG-2 cRstmNaF None

[Bianco]

A few things that come into mind:

Is JTAG wired correctly?

Is the exposed pad connected properly to ground?

Do you have proper power supply sequencing?

Even without a clock signal it should show [ L0 ] i believe

[XMatt]

To expand a little on bianco's post, a couple of notes that may help,

xrun -l reports none when it is unable to identify devices on the JTAG chain. This could be an issue with JTAG chain wiring on your board or something more fundamental such as the device not being powered correctly.

There is some help here on the XMOS FAQ for items to check with regards to correct operation with the tools, I apologise for some of the formatting issues I will get that corrected but the information maybe useful to you.

http://www.xmos.com/support/knowledgeba ... ion=latest

[eladmmor]

First of all hi and thanks for your helpful comments.

Bianco:
JTAG must be connected correctly because it identifies the Reference design board which I also have. The board connectivity layout should be correct but I will look into it again.

By the exposed pad you mean pin 49 (the big square in the bottom of the Xs1-l1-48)?
If the answer is yes, than it should be grounded (unless the solderer was mistaken).

The power sequencing scheme was copied in full from the reference design using the exact same component so I would gamble the problem is not there.

XMatt:
Thanks for mentioned article - I'll look into it soon.

BTW - I have a feeling something in the soldering of the XMOS itself is wrong (there was a slight error in the main pitch of the XMOS footprint).
I find it hard to verify that is the problem.. Any ideas for how to make sure this is the problem?

Thanks again
Elad

[Bianco]

First of all hi and thanks for your helpful comments.

Bianco:
JTAG must be connected correctly because it identifies the Reference design board which I also have. The board connectivity layout should be correct but I will look into it again.

By the exposed pad you mean pin 49 (the big square in the bottom of the Xs1-l1-48)?
If the answer is yes, than it should be grounded (unless the solderer was mistaken).

The power sequencing scheme was copied in full from the reference design using the exact same component so I would gamble the problem is not there.

XMatt:
Thanks for mentioned article - I'll look into it soon.

BTW - I have a feeling something in the soldering of the XMOS itself is wrong (there was a slight error in the main pitch of the XMOS footprint).
I find it hard to verify that is the problem.. Any ideas for how to make sure this is the problem?

Thanks again
Elad

It is still a good idea to check the important things like supply sequencing with a scope just to be sure.

If your footprint is slightly off you should be able to get somewhere using a good magnifier or microscope. I also often take pictures with a digital camera in macro mode to further analyze it on a PC.

Can you confirm that you see some wire toggling on TDO (TDSNK pin on the XTAG2) when running "xrun -l"?

Do you use buffers on the JTAG lines? If not correctly applied they can cause problems too, you should be able to confirm this with probing with a scope

[eladmmor]

Good news guys!!

I've managed to access the chip from the XDE!

The problem was improper physical connection between the pad and chip leg of "TCK".

Thanks for the help.

Regards,
Elad