Inconsistency in Slicekit Port/Slot Mapping

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
asibbald
Member
Posts: 11
Joined: Thu Jan 07, 2010 1:56 am

Inconsistency in Slicekit Port/Slot Mapping

Post by asibbald »

A question for XMOS:

On your webpage regarding the slicekit ( here: https://www.xmos.com/node/16091?page=1 ), you have a list of L2 pin / Slot / Function, and then further down the page a series of lists of slot pinouts for each of the slots.

I have spotted an inconsistency in these lists:

In the first list, you have:

X0D3 goes to Star B7 and Chain A6
X0D5 goes to Star B11 and Chain A9

But then in the Star Table, you have

B7 connects to X0D3
as well as
B11 connects to X0D3

In the Chain Table, you have:

A6 connects to X0D3
A9 connects to X0D5

At a guess, the listing in the star table for B11 is incorrect and should state:

B11 connects to X0D5

Could you confirm which is correct??